Re: [PATCH v3 2/3] target/riscv: add query-cpy-definitions support

[Alistair Francis <alistair23@gmail.com>]

On Wed, Apr 12, 2023 at 4:37 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> This command is used by tooling like libvirt to retrieve a list of
> supported CPUs. Each entry returns a CpuDefinitionInfo object that
> contains more information about each CPU.
>
> This initial support includes only the name of the CPU and its typename.
> Here's what the command produces for the riscv64 target:
>
> $ ./build/qemu-system-riscv64 -S -M virt -display none -qmp stdio
> {"QMP": {"version": (...)}
> {"execute": "qmp_capabilities", "arguments": {"enable": ["oob"]}}
> {"return": {}}
> {"execute": "query-cpu-definitions"}
> {"return": [
> {"name": "rv64", "typename": "rv64-riscv-cpu", "static": false, "deprecated": false},
> {"name": "sifive-e51", "typename": "sifive-e51-riscv-cpu", "static": false, "deprecated": false},
> {"name": "any", "typename": "any-riscv-cpu", "static": false, "deprecated": false},
> {"name": "x-rv128", "typename": "x-rv128-riscv-cpu", "static": false, "deprecated": false},
> {"name": "shakti-c", "typename": "shakti-c-riscv-cpu", "static": false, "deprecated": false},
> {"name": "thead-c906", "typename": "thead-c906-riscv-cpu", "static": false, "deprecated": false},
> {"name": "sifive-u54", "typename": "sifive-u54-riscv-cpu", "static": false, "deprecated": false}]
> }
>
> Next patch will introduce a way to tell whether a given CPU is static or
> not.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  qapi/machine-target.json      |  6 ++--
>  target/riscv/meson.build      |  3 +-
>  target/riscv/riscv-qmp-cmds.c | 53 +++++++++++++++++++++++++++++++++++
>  3 files changed, 59 insertions(+), 3 deletions(-)
>  create mode 100644 target/riscv/riscv-qmp-cmds.c
>
> diff --git a/qapi/machine-target.json b/qapi/machine-target.json
> index 2e267fa458..f3a3de6648 100644
> --- a/qapi/machine-target.json
> +++ b/qapi/machine-target.json
> @@ -324,7 +324,8 @@
>                     'TARGET_I386',
>                     'TARGET_S390X',
>                     'TARGET_MIPS',
> -                   'TARGET_LOONGARCH64' ] } }
> +                   'TARGET_LOONGARCH64',
> +                   'TARGET_RISCV' ] } }
>
>  ##
>  # @query-cpu-definitions:
> @@ -341,4 +342,5 @@
>                     'TARGET_I386',
>                     'TARGET_S390X',
>                     'TARGET_MIPS',
> -                   'TARGET_LOONGARCH64' ] } }
> +                   'TARGET_LOONGARCH64',
> +                   'TARGET_RISCV' ] } }
> diff --git a/target/riscv/meson.build b/target/riscv/meson.build
> index 5b7f813a3e..e1ff6d9b95 100644
> --- a/target/riscv/meson.build
> +++ b/target/riscv/meson.build
> @@ -32,7 +32,8 @@ riscv_softmmu_ss.add(files(
>    'monitor.c',
>    'machine.c',
>    'pmu.c',
> -  'time_helper.c'
> +  'time_helper.c',
> +  'riscv-qmp-cmds.c',
>  ))
>
>  target_arch += {'riscv': riscv_ss}
> diff --git a/target/riscv/riscv-qmp-cmds.c b/target/riscv/riscv-qmp-cmds.c
> new file mode 100644
> index 0000000000..128677add9
> --- /dev/null
> +++ b/target/riscv/riscv-qmp-cmds.c
> @@ -0,0 +1,53 @@
> +/*
> + * QEMU CPU QMP commands for RISC-V
> + *
> + * Copyright (c) 2023 Ventana Micro Systems Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#include "qemu/osdep.h"
> +
> +#include "qapi/qapi-commands-machine-target.h"
> +#include "cpu-qom.h"
> +
> +static void riscv_cpu_add_definition(gpointer data, gpointer user_data)
> +{
> +    ObjectClass *oc = data;
> +    CpuDefinitionInfoList **cpu_list = user_data;
> +    CpuDefinitionInfo *info = g_malloc0(sizeof(*info));
> +    const char *typename = object_class_get_name(oc);
> +
> +    info->name = g_strndup(typename,
> +                           strlen(typename) - strlen("-" TYPE_RISCV_CPU));
> +    info->q_typename = g_strdup(typename);
> +
> +    QAPI_LIST_PREPEND(*cpu_list, info);
> +}
> +
> +CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
> +{
> +    CpuDefinitionInfoList *cpu_list = NULL;
> +    GSList *list = object_class_get_list(TYPE_RISCV_CPU, false);
> +
> +    g_slist_foreach(list, riscv_cpu_add_definition, &cpu_list);
> +    g_slist_free(list);
> +
> +    return cpu_list;
> +}
> --
> 2.39.2
>
>