From: Alistair Francis <alistair23@gmail.com>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Palmer Dabbelt <palmer@sifive.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH v5 06/30] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h
Date: Fri, 23 Aug 2019 10:38:13 -0700 [thread overview]
Message-ID: <CAKmqyKNuQN9X4VLc3e8vhNrBjg=+tKTJHikSy4QAX8m0FKSp0g@mail.gmail.com> (raw)
In-Reply-To: <1566537069-22741-7-git-send-email-bmeng.cn@gmail.com>
On Thu, Aug 22, 2019 at 10:21 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> The inclusion of "target/riscv/cpu.h" is unnecessary in various
> sifive model drivers.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
>
> ---
>
> Changes in v5:
> - new patch to remove the unnecessary include of target/riscv/cpu.h
>
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
>
> hw/riscv/sifive_prci.c | 1 -
> hw/riscv/sifive_test.c | 1 -
> hw/riscv/sifive_uart.c | 1 -
> 3 files changed, 3 deletions(-)
>
> diff --git a/hw/riscv/sifive_prci.c b/hw/riscv/sifive_prci.c
> index 1ab98d4..1957dcd 100644
> --- a/hw/riscv/sifive_prci.c
> +++ b/hw/riscv/sifive_prci.c
> @@ -22,7 +22,6 @@
> #include "hw/sysbus.h"
> #include "qemu/log.h"
> #include "qemu/module.h"
> -#include "target/riscv/cpu.h"
> #include "hw/riscv/sifive_prci.h"
>
> static uint64_t sifive_prci_read(void *opaque, hwaddr addr, unsigned int size)
> diff --git a/hw/riscv/sifive_test.c b/hw/riscv/sifive_test.c
> index 655a3d7..31cad9f 100644
> --- a/hw/riscv/sifive_test.c
> +++ b/hw/riscv/sifive_test.c
> @@ -23,7 +23,6 @@
> #include "qemu/log.h"
> #include "qemu/module.h"
> #include "sysemu/sysemu.h"
> -#include "target/riscv/cpu.h"
> #include "hw/riscv/sifive_test.h"
>
> static uint64_t sifive_test_read(void *opaque, hwaddr addr, unsigned int size)
> diff --git a/hw/riscv/sifive_uart.c b/hw/riscv/sifive_uart.c
> index cd74043..1601bd9 100644
> --- a/hw/riscv/sifive_uart.c
> +++ b/hw/riscv/sifive_uart.c
> @@ -22,7 +22,6 @@
> #include "hw/sysbus.h"
> #include "chardev/char.h"
> #include "chardev/char-fe.h"
> -#include "target/riscv/cpu.h"
> #include "hw/riscv/sifive_uart.h"
>
> /*
> --
> 2.7.4
>
>
next prev parent reply other threads:[~2019-08-23 17:48 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-23 5:10 [Qemu-devel] [PATCH v5 00/30] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine Bin Meng
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 01/30] riscv: hw: Remove superfluous "linux, phandle" property Bin Meng
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 02/30] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell Bin Meng
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 03/30] riscv: hw: Remove not needed PLIC properties in device tree Bin Meng
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 04/30] riscv: hw: Change create_fdt() to return void Bin Meng
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 05/30] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead Bin Meng
2019-08-23 17:38 ` Alistair Francis
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 06/30] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h Bin Meng
2019-08-23 17:38 ` Alistair Francis [this message]
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 07/30] riscv: roms: Remove executable attribute of opensbi images Bin Meng
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 08/30] riscv: sifive_u: Remove the unnecessary include of prci header Bin Meng
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 09/30] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} Bin Meng
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 10/30] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming Bin Meng
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 11/30] riscv: sifive_e: prci: Update the PRCI register block size Bin Meng
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 13/30] riscv: Add a sifive_cpu.h to include both E and U cpu type defines Bin Meng
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 14/30] riscv: hart: Extract hart realize to a separate routine Bin Meng
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 15/30] riscv: hart: Add a "hartid-base" property to RISC-V hart array Bin Meng
2019-08-23 18:31 ` Alistair Francis
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 16/30] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC Bin Meng
2019-08-23 17:36 ` Alistair Francis
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 17/30] riscv: sifive_u: Set the minimum number of cpus to 2 Bin Meng
2019-08-23 18:34 ` Alistair Francis
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 18/30] riscv: sifive_u: Update PLIC hart topology configuration string Bin Meng
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 19/30] riscv: sifive: Implement PRCI model for FU540 Bin Meng
2019-08-23 23:45 ` Alistair Francis
2019-08-23 5:10 ` [Qemu-devel] [PATCH v5 20/30] riscv: sifive_u: Generate hfclk and rtcclk nodes Bin Meng
2019-08-23 5:11 ` [Qemu-devel] [PATCH v5 21/30] riscv: sifive_u: Add PRCI block to the SoC Bin Meng
2019-08-23 23:52 ` Alistair Francis
2019-08-23 5:11 ` [Qemu-devel] [PATCH v5 22/30] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes Bin Meng
2019-08-23 5:11 ` [Qemu-devel] [PATCH v5 23/30] riscv: sifive_u: Update UART base addresses and IRQs Bin Meng
2019-08-23 5:11 ` [Qemu-devel] [PATCH v5 24/30] riscv: sifive_u: Change UART node name in device tree Bin Meng
2019-08-23 5:11 ` [Qemu-devel] [PATCH v5 25/30] riscv: roms: Update default bios for sifive_u machine Bin Meng
2019-08-23 5:11 ` [Qemu-devel] [PATCH v5 26/30] riscv: sifive: Implement a model for SiFive FU540 OTP Bin Meng
2019-08-23 5:11 ` [Qemu-devel] [PATCH v5 28/30] riscv: sifive_u: Fix broken GEM support Bin Meng
2019-08-23 5:11 ` [Qemu-devel] [PATCH v5 29/30] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet Bin Meng
2019-08-23 5:11 ` [Qemu-devel] [PATCH v5 30/30] riscv: sifive_u: Update model and compatible strings in device tree Bin Meng
2019-08-23 17:24 ` [Qemu-devel] [PATCH v5 00/30] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine Alistair Francis
2019-08-24 5:07 ` Bin Meng
2019-08-26 21:33 ` Alistair Francis
2019-08-23 17:40 ` Alistair Francis
[not found] ` <1566537069-22741-13-git-send-email-bmeng.cn@gmail.com>
2019-08-26 21:36 ` [Qemu-devel] [PATCH v5 12/30] riscv: sifive_e: Drop sifive_mmio_emulate() Alistair Francis
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='CAKmqyKNuQN9X4VLc3e8vhNrBjg=+tKTJHikSy4QAX8m0FKSp0g@mail.gmail.com' \
--to=alistair23@gmail.com \
--cc=Alistair.Francis@wdc.com \
--cc=bmeng.cn@gmail.com \
--cc=palmer@sifive.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).