* [Qemu-devel] [PATCH v2 2/4] disas/riscv: Disassemble reserved compressed encodings as illegal
2019-06-24 23:42 [Qemu-devel] [PATCH v2 0/4] Miscellaneous patches from the RISC-V fork Alistair Francis
2019-06-24 23:42 ` [Qemu-devel] [PATCH v2 1/4] target/riscv: Fix PMP range boundary address bug Alistair Francis
@ 2019-06-24 23:42 ` Alistair Francis
2019-06-24 23:42 ` [Qemu-devel] [PATCH v2 3/4] disas/riscv: Fix `rdinstreth` constraint Alistair Francis
` (3 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Alistair Francis @ 2019-06-24 23:42 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair23, palmer, alistair.francis
From: Michael Clark <mjc@sifive.com>
Due to the design of the disassembler, the immediate is not
known during decoding of the opcode; so to handle compressed
encodings with reserved immediate values (non-zero), we need
to add an additional check during decompression to match
reserved encodings with zero immediates and translate them
into the illegal instruction.
The following compressed opcodes have reserved encodings with
zero immediates: c.addi4spn, c.addi, c.lui, c.addi16sp, c.srli,
c.srai, c.andi and c.slli
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
disas/riscv.c | 51 ++++++++++++++++++++++++++++++++++-----------------
1 file changed, 34 insertions(+), 17 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 59a9b0437a..3ab4586f0a 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -504,14 +504,19 @@ typedef struct {
const rvc_constraint *constraints;
} rv_comp_data;
+enum {
+ rvcd_imm_nz = 0x1
+};
+
typedef struct {
const char * const name;
const rv_codec codec;
const char * const format;
const rv_comp_data *pseudo;
- const int decomp_rv32;
- const int decomp_rv64;
- const int decomp_rv128;
+ const short decomp_rv32;
+ const short decomp_rv64;
+ const short decomp_rv128;
+ const short decomp_data;
} rv_opcode_data;
/* register names */
@@ -1011,7 +1016,7 @@ const rv_opcode_data opcode_data[] = {
{ "fcvt.q.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
{ "fmv.x.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
{ "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 },
- { "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, rv_op_addi },
+ { "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, rv_op_addi, rvcd_imm_nz },
{ "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, NULL, rv_op_fld, rv_op_fld, 0 },
{ "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw, rv_op_lw },
{ "c.flw", rv_codec_cl_lw, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, 0 },
@@ -1019,14 +1024,14 @@ const rv_opcode_data opcode_data[] = {
{ "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw, rv_op_sw },
{ "c.fsw", rv_codec_cs_sw, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, 0 },
{ "c.nop", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_addi, rv_op_addi, rv_op_addi },
- { "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, rv_op_addi },
+ { "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, rv_op_addi, rvcd_imm_nz },
{ "c.jal", rv_codec_cj_jal, rv_fmt_rd_offset, NULL, rv_op_jal, 0, 0 },
{ "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, rv_op_addi },
- { "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, rv_op_addi },
- { "c.lui", rv_codec_ci_lui, rv_fmt_rd_imm, NULL, rv_op_lui, rv_op_lui, rv_op_lui },
- { "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srli, rv_op_srli, rv_op_srli },
- { "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srai, rv_op_srai, rv_op_srai },
- { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL, rv_op_andi, rv_op_andi, rv_op_andi },
+ { "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, rv_op_addi, rvcd_imm_nz },
+ { "c.lui", rv_codec_ci_lui, rv_fmt_rd_imm, NULL, rv_op_lui, rv_op_lui, rv_op_lui, rvcd_imm_nz },
+ { "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srli, rv_op_srli, rv_op_srli, rvcd_imm_nz },
+ { "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srai, rv_op_srai, rv_op_srai, rvcd_imm_nz },
+ { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL, rv_op_andi, rv_op_andi, rv_op_andi, rvcd_imm_nz },
{ "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub, rv_op_sub, rv_op_sub },
{ "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_xor, rv_op_xor, rv_op_xor },
{ "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_or, rv_op_or, rv_op_or },
@@ -1036,7 +1041,7 @@ const rv_opcode_data opcode_data[] = {
{ "c.j", rv_codec_cj, rv_fmt_rd_offset, NULL, rv_op_jal, rv_op_jal, rv_op_jal },
{ "c.beqz", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_beq, rv_op_beq, rv_op_beq },
{ "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_bne, rv_op_bne, rv_op_bne },
- { "c.slli", rv_codec_ci_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_slli, rv_op_slli, rv_op_slli },
+ { "c.slli", rv_codec_ci_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_slli, rv_op_slli, rv_op_slli, rvcd_imm_nz },
{ "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1, NULL, rv_op_fld, rv_op_fld, rv_op_fld },
{ "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw, rv_op_lw },
{ "c.flwsp", rv_codec_ci_lwsp, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, 0 },
@@ -2795,8 +2800,12 @@ static void decode_inst_decompress_rv32(rv_decode *dec)
{
int decomp_op = opcode_data[dec->op].decomp_rv32;
if (decomp_op != rv_op_illegal) {
- dec->op = decomp_op;
- dec->codec = opcode_data[decomp_op].codec;
+ if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz) && dec->imm == 0) {
+ dec->op = rv_op_illegal;
+ } else {
+ dec->op = decomp_op;
+ dec->codec = opcode_data[decomp_op].codec;
+ }
}
}
@@ -2804,8 +2813,12 @@ static void decode_inst_decompress_rv64(rv_decode *dec)
{
int decomp_op = opcode_data[dec->op].decomp_rv64;
if (decomp_op != rv_op_illegal) {
- dec->op = decomp_op;
- dec->codec = opcode_data[decomp_op].codec;
+ if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz) && dec->imm == 0) {
+ dec->op = rv_op_illegal;
+ } else {
+ dec->op = decomp_op;
+ dec->codec = opcode_data[decomp_op].codec;
+ }
}
}
@@ -2813,8 +2826,12 @@ static void decode_inst_decompress_rv128(rv_decode *dec)
{
int decomp_op = opcode_data[dec->op].decomp_rv128;
if (decomp_op != rv_op_illegal) {
- dec->op = decomp_op;
- dec->codec = opcode_data[decomp_op].codec;
+ if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz) && dec->imm == 0) {
+ dec->op = rv_op_illegal;
+ } else {
+ dec->op = decomp_op;
+ dec->codec = opcode_data[decomp_op].codec;
+ }
}
}
--
2.22.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [Qemu-devel] [PATCH v2 3/4] disas/riscv: Fix `rdinstreth` constraint
2019-06-24 23:42 [Qemu-devel] [PATCH v2 0/4] Miscellaneous patches from the RISC-V fork Alistair Francis
2019-06-24 23:42 ` [Qemu-devel] [PATCH v2 1/4] target/riscv: Fix PMP range boundary address bug Alistair Francis
2019-06-24 23:42 ` [Qemu-devel] [PATCH v2 2/4] disas/riscv: Disassemble reserved compressed encodings as illegal Alistair Francis
@ 2019-06-24 23:42 ` Alistair Francis
2019-06-24 23:42 ` [Qemu-devel] [PATCH v2 4/4] target/riscv: Implement riscv_cpu_unassigned_access Alistair Francis
` (2 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Alistair Francis @ 2019-06-24 23:42 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair23, palmer, alistair.francis
From: Michael Clark <mjc@sifive.com>
The constraint for `rdinstreth` was comparing the csr number to 0xc80,
which is `cycleh` instead. Fix this.
Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
disas/riscv.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 3ab4586f0a..bdcc70a68e 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -614,7 +614,7 @@ static const rvc_constraint rvcc_rdtime[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc01, r
static const rvc_constraint rvcc_rdinstret[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc02, rvc_end };
static const rvc_constraint rvcc_rdcycleh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc80, rvc_end };
static const rvc_constraint rvcc_rdtimeh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc81, rvc_end };
-static const rvc_constraint rvcc_rdinstreth[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc80, rvc_end };
+static const rvc_constraint rvcc_rdinstreth[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc82, rvc_end };
static const rvc_constraint rvcc_frcsr[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x003, rvc_end };
static const rvc_constraint rvcc_frrm[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x002, rvc_end };
static const rvc_constraint rvcc_frflags[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x001, rvc_end };
@@ -1031,7 +1031,7 @@ const rv_opcode_data opcode_data[] = {
{ "c.lui", rv_codec_ci_lui, rv_fmt_rd_imm, NULL, rv_op_lui, rv_op_lui, rv_op_lui, rvcd_imm_nz },
{ "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srli, rv_op_srli, rv_op_srli, rvcd_imm_nz },
{ "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srai, rv_op_srai, rv_op_srai, rvcd_imm_nz },
- { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL, rv_op_andi, rv_op_andi, rv_op_andi, rvcd_imm_nz },
+ { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL, rv_op_andi, rv_op_andi, rv_op_andi },
{ "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub, rv_op_sub, rv_op_sub },
{ "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_xor, rv_op_xor, rv_op_xor },
{ "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_or, rv_op_or, rv_op_or },
--
2.22.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [Qemu-devel] [PATCH v2 0/4] Miscellaneous patches from the RISC-V fork
2019-06-24 23:42 [Qemu-devel] [PATCH v2 0/4] Miscellaneous patches from the RISC-V fork Alistair Francis
` (3 preceding siblings ...)
2019-06-24 23:42 ` [Qemu-devel] [PATCH v2 4/4] target/riscv: Implement riscv_cpu_unassigned_access Alistair Francis
@ 2019-06-25 1:14 ` no-reply
2019-06-25 10:20 ` Palmer Dabbelt
5 siblings, 0 replies; 7+ messages in thread
From: no-reply @ 2019-06-25 1:14 UTC (permalink / raw)
To: alistair.francis
Cc: alistair23, alistair.francis, palmer, qemu-riscv, qemu-devel
Patchew URL: https://patchew.org/QEMU/cover.1561419713.git.alistair.francis@wdc.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: cover.1561419713.git.alistair.francis@wdc.com
Type: series
Subject: [Qemu-devel] [PATCH v2 0/4] Miscellaneous patches from the RISC-V fork
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
From https://github.com/patchew-project/qemu
* [new tag] patchew/cover.1561419713.git.alistair.francis@wdc.com -> patchew/cover.1561419713.git.alistair.francis@wdc.com
Switched to a new branch 'test'
ea39509 target/riscv: Implement riscv_cpu_unassigned_access
e1ca264 disas/riscv: Fix `rdinstreth` constraint
6e119a5 disas/riscv: Disassemble reserved compressed encodings as illegal
eb4b804 target/riscv: Fix PMP range boundary address bug
=== OUTPUT BEGIN ===
1/4 Checking commit eb4b80481b1a (target/riscv: Fix PMP range boundary address bug)
2/4 Checking commit 6e119a562b35 (disas/riscv: Disassemble reserved compressed encodings as illegal)
ERROR: line over 90 characters
#54: FILE: disas/riscv.c:1019:
+ { "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, rv_op_addi, rvcd_imm_nz },
ERROR: line over 90 characters
#63: FILE: disas/riscv.c:1027:
+ { "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, rv_op_addi, rvcd_imm_nz },
ERROR: line over 90 characters
#71: FILE: disas/riscv.c:1030:
+ { "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, rv_op_addi, rvcd_imm_nz },
ERROR: line over 90 characters
#72: FILE: disas/riscv.c:1031:
+ { "c.lui", rv_codec_ci_lui, rv_fmt_rd_imm, NULL, rv_op_lui, rv_op_lui, rv_op_lui, rvcd_imm_nz },
ERROR: line over 90 characters
#73: FILE: disas/riscv.c:1032:
+ { "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srli, rv_op_srli, rv_op_srli, rvcd_imm_nz },
ERROR: line over 90 characters
#74: FILE: disas/riscv.c:1033:
+ { "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srai, rv_op_srai, rv_op_srai, rvcd_imm_nz },
ERROR: line over 90 characters
#75: FILE: disas/riscv.c:1034:
+ { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL, rv_op_andi, rv_op_andi, rv_op_andi, rvcd_imm_nz },
ERROR: line over 90 characters
#84: FILE: disas/riscv.c:1044:
+ { "c.slli", rv_codec_ci_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_slli, rv_op_slli, rv_op_slli, rvcd_imm_nz },
total: 8 errors, 0 warnings, 100 lines checked
Patch 2/4 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/4 Checking commit e1ca26481ca9 (disas/riscv: Fix `rdinstreth` constraint)
ERROR: line over 90 characters
#24: FILE: disas/riscv.c:617:
+static const rvc_constraint rvcc_rdinstreth[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc82, rvc_end };
ERROR: line over 90 characters
#33: FILE: disas/riscv.c:1034:
+ { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL, rv_op_andi, rv_op_andi, rv_op_andi },
total: 2 errors, 0 warnings, 16 lines checked
Patch 3/4 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
4/4 Checking commit ea39509e914c (target/riscv: Implement riscv_cpu_unassigned_access)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/cover.1561419713.git.alistair.francis@wdc.com/testing.checkpatch/?type=message.
---
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Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 7+ messages in thread