From: Palmer Dabbelt <palmer@sifive.com>
To: Alistair Francis <Alistair.Francis@wdc.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
alistair23@gmail.com
Subject: Re: [Qemu-devel] [PATCH v1 4/4] target/riscv: Implement riscv_cpu_unassigned_access
Date: Fri, 14 Jun 2019 02:41:16 -0700 (PDT) [thread overview]
Message-ID: <mhng-d2259f3e-29d6-47f5-b6a8-7b9224ae7a4e@palmer-si-x1e> (raw)
In-Reply-To: <7e9b4a6cc07a931e62da9c18c40849690eef7150.1558131003.git.alistair.francis@wdc.com>
On Fri, 17 May 2019 15:11:06 PDT (-0700), Alistair Francis wrote:
> From: Michael Clark <mjc@sifive.com>
>
> This patch adds support for the riscv_cpu_unassigned_access call
> and will raise a load or store access fault.
>
> Signed-off-by: Michael Clark <mjc@sifive.com>
> [Changes by AF:
> - Squash two patches and rewrite commit message
> - Set baddr to the access address
> ]
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/cpu.c | 1 +
> target/riscv/cpu.h | 2 ++
> target/riscv/cpu_helper.c | 16 ++++++++++++++++
> 3 files changed, 19 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index b7675707e0..bfe92235d3 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -356,6 +356,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
> cc->gdb_stop_before_watchpoint = true;
> cc->disas_set_info = riscv_cpu_disas_set_info;
> #ifndef CONFIG_USER_ONLY
> + cc->do_unassigned_access = riscv_cpu_unassigned_access;
> cc->do_unaligned_access = riscv_cpu_do_unaligned_access;
> cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
> #endif
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index c17184f4e4..8250175811 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -264,6 +264,8 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
> bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> MMUAccessType access_type, int mmu_idx,
> bool probe, uintptr_t retaddr);
> +void riscv_cpu_unassigned_access(CPUState *cpu, hwaddr addr, bool is_write,
> + bool is_exec, int unused, unsigned size);
> char *riscv_isa_string(RISCVCPU *cpu);
> void riscv_cpu_list(void);
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 41d6db41c3..202b6f021d 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -356,6 +356,22 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
> return phys_addr;
> }
>
> +void riscv_cpu_unassigned_access(CPUState *cs, hwaddr addr, bool is_write,
> + bool is_exec, int unused, unsigned size)
> +{
> + RISCVCPU *cpu = RISCV_CPU(cs);
> + CPURISCVState *env = &cpu->env;
> +
> + if (is_write) {
> + cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
> + } else {
> + cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
> + }
> +
> + env->badaddr = addr;
> + riscv_raise_exception(&cpu->env, cs->exception_index, GETPC());
> +}
> +
> void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
> MMUAccessType access_type, int mmu_idx,
> uintptr_t retaddr)
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
next prev parent reply other threads:[~2019-06-14 9:58 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-17 22:10 [Qemu-devel] [PATCH v1 0/4] Miscellaneous patches from the RISC-V fork Alistair Francis
2019-05-17 22:10 ` [Qemu-devel] [PATCH v1 1/4] target/riscv: Fix PMP range boundary address bug Alistair Francis
2019-05-17 22:11 ` [Qemu-devel] [PATCH v1 2/4] disas/riscv: Disassemble reserved compressed encodings as illegal Alistair Francis
2019-06-14 9:18 ` Palmer Dabbelt
2019-06-19 20:26 ` Alistair Francis
2019-05-17 22:11 ` [Qemu-devel] [PATCH v1 3/4] disas/riscv: Fix `rdinstreth` constraint Alistair Francis
2019-06-14 9:41 ` Palmer Dabbelt
2019-06-17 17:05 ` Alistair Francis
2019-05-17 22:11 ` [Qemu-devel] [PATCH v1 4/4] target/riscv: Implement riscv_cpu_unassigned_access Alistair Francis
2019-06-14 9:41 ` Palmer Dabbelt [this message]
2019-06-06 18:41 ` [Qemu-devel] [PATCH v1 0/4] Miscellaneous patches from the RISC-V fork Alistair Francis
2019-06-14 9:46 ` Palmer Dabbelt
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