From: Kishon Vijay Abraham I <kishon@ti.com> To: Kishon Vijay Abraham I <kishon@ti.com>, Vinod Koul <vkoul@kernel.org>, Rob Herring <robh+dt@kernel.org>, Peter Rosin <peda@axentia.se>, Swapnil Jakhade <sjakhade@cadence.com> Cc: <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-phy@lists.infradead.org> Subject: [PATCH v2 0/9] AM64: Add SERDES bindings and driver support Date: Mon, 22 Feb 2021 16:53:05 +0530 [thread overview] Message-ID: <20210222112314.10772-1-kishon@ti.com> (raw) AM64 uses the same SERDES as in J7200, however AM642 EVM doesn't have a clock generator (unlike J7200 base board). Here the clock from the SERDES has to be routed to the PCIE connector. This series adds support to drive reference clock output from SERDES and also adds SERDES (torrent) and SERDES wrapper (WIZ) bindings. v1 of the patch series can be found @ [1] Changes from v1: *) Model the internal clocks without device tree input (Add #clock-cells to SERDES DT nodes for getting a reference to the clock using index to phandle). This is in accordance with comment given by Rob [2]. However the existing method to model clocks from device tree is not removed to support upstreamed device tree. *) Included a patch to fix modifying static data by instance specific initializations. *) Added a fix to delete "clk_div_sel" clk provider during cleanup [1] -> https://lore.kernel.org/r/20201224114250.1083-1-kishon@ti.com [2] -> http://lore.kernel.org/r/20210108025943.GA1790601@robh.at.kernel.org Kishon Vijay Abraham I (9): dt-bindings: phy: ti,phy-j721e-wiz: Add bindings for AM64 SERDES Wrapper dt-bindings: phy: cadence-torrent: Add binding for refclk driver dt-bindings: ti-serdes-mux: Add defines for AM64 SoC phy: ti: j721e-wiz: Remove "regmap_field" from wiz_clk_{mux|div}_sel phy: ti: j721e-wiz: Delete "clk_div_sel" clk provider during cleanup phy: ti: j721e-wiz: Configure full rate divider for AM64 phy: ti: j721e-wiz: Model the internal clocks without device tree input phy: ti: j721e-wiz: Enable reference clock output in cmn_refclk_<p/m> phy: cadence-torrent: Add support to drive refclk out .../bindings/phy/phy-cadence-torrent.yaml | 20 +- .../bindings/phy/ti,phy-j721e-wiz.yaml | 10 +- drivers/phy/cadence/phy-cadence-torrent.c | 202 +++++++++- drivers/phy/ti/phy-j721e-wiz.c | 349 +++++++++++++++--- include/dt-bindings/mux/ti-serdes.h | 5 + include/dt-bindings/phy/phy-cadence-torrent.h | 2 + include/dt-bindings/phy/phy-ti.h | 21 ++ 7 files changed, 553 insertions(+), 56 deletions(-) create mode 100644 include/dt-bindings/phy/phy-ti.h -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Kishon Vijay Abraham I <kishon@ti.com> To: Kishon Vijay Abraham I <kishon@ti.com>, Vinod Koul <vkoul@kernel.org>, Rob Herring <robh+dt@kernel.org>, Peter Rosin <peda@axentia.se>, Swapnil Jakhade <sjakhade@cadence.com> Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 0/9] AM64: Add SERDES bindings and driver support Date: Mon, 22 Feb 2021 16:53:05 +0530 [thread overview] Message-ID: <20210222112314.10772-1-kishon@ti.com> (raw) AM64 uses the same SERDES as in J7200, however AM642 EVM doesn't have a clock generator (unlike J7200 base board). Here the clock from the SERDES has to be routed to the PCIE connector. This series adds support to drive reference clock output from SERDES and also adds SERDES (torrent) and SERDES wrapper (WIZ) bindings. v1 of the patch series can be found @ [1] Changes from v1: *) Model the internal clocks without device tree input (Add #clock-cells to SERDES DT nodes for getting a reference to the clock using index to phandle). This is in accordance with comment given by Rob [2]. However the existing method to model clocks from device tree is not removed to support upstreamed device tree. *) Included a patch to fix modifying static data by instance specific initializations. *) Added a fix to delete "clk_div_sel" clk provider during cleanup [1] -> https://lore.kernel.org/r/20201224114250.1083-1-kishon@ti.com [2] -> http://lore.kernel.org/r/20210108025943.GA1790601@robh.at.kernel.org Kishon Vijay Abraham I (9): dt-bindings: phy: ti,phy-j721e-wiz: Add bindings for AM64 SERDES Wrapper dt-bindings: phy: cadence-torrent: Add binding for refclk driver dt-bindings: ti-serdes-mux: Add defines for AM64 SoC phy: ti: j721e-wiz: Remove "regmap_field" from wiz_clk_{mux|div}_sel phy: ti: j721e-wiz: Delete "clk_div_sel" clk provider during cleanup phy: ti: j721e-wiz: Configure full rate divider for AM64 phy: ti: j721e-wiz: Model the internal clocks without device tree input phy: ti: j721e-wiz: Enable reference clock output in cmn_refclk_<p/m> phy: cadence-torrent: Add support to drive refclk out .../bindings/phy/phy-cadence-torrent.yaml | 20 +- .../bindings/phy/ti,phy-j721e-wiz.yaml | 10 +- drivers/phy/cadence/phy-cadence-torrent.c | 202 +++++++++- drivers/phy/ti/phy-j721e-wiz.c | 349 +++++++++++++++--- include/dt-bindings/mux/ti-serdes.h | 5 + include/dt-bindings/phy/phy-cadence-torrent.h | 2 + include/dt-bindings/phy/phy-ti.h | 21 ++ 7 files changed, 553 insertions(+), 56 deletions(-) create mode 100644 include/dt-bindings/phy/phy-ti.h -- 2.17.1 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy
next reply other threads:[~2021-02-22 11:25 UTC|newest] Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-02-22 11:23 Kishon Vijay Abraham I [this message] 2021-02-22 11:23 ` [PATCH v2 0/9] AM64: Add SERDES bindings and driver support Kishon Vijay Abraham I 2021-02-22 11:23 ` [PATCH v2 1/9] dt-bindings: phy: ti,phy-j721e-wiz: Add bindings for AM64 SERDES Wrapper Kishon Vijay Abraham I 2021-02-22 11:23 ` [PATCH v2 1/9] dt-bindings: phy: ti, phy-j721e-wiz: " Kishon Vijay Abraham I 2021-03-04 4:45 ` [PATCH v2 1/9] dt-bindings: phy: ti,phy-j721e-wiz: " Kishon Vijay Abraham I 2021-03-04 4:45 ` Kishon Vijay Abraham I 2021-03-08 17:50 ` Rob Herring 2021-03-08 17:50 ` Rob Herring 2021-02-22 11:23 ` [PATCH v2 2/9] dt-bindings: phy: cadence-torrent: Add binding for refclk driver Kishon Vijay Abraham I 2021-02-22 11:23 ` Kishon Vijay Abraham I 2021-03-08 17:51 ` Rob Herring 2021-03-08 17:51 ` Rob Herring 2021-02-22 11:23 ` [PATCH v2 3/9] dt-bindings: ti-serdes-mux: Add defines for AM64 SoC Kishon Vijay Abraham I 2021-02-22 11:23 ` Kishon Vijay Abraham I 2021-03-08 17:52 ` Rob Herring 2021-03-08 17:52 ` Rob Herring 2021-02-22 11:23 ` [PATCH v2 4/9] phy: ti: j721e-wiz: Remove "regmap_field" from wiz_clk_{mux|div}_sel Kishon Vijay Abraham I 2021-02-22 11:23 ` Kishon Vijay Abraham I 2021-02-22 11:23 ` [PATCH v2 5/9] phy: ti: j721e-wiz: Delete "clk_div_sel" clk provider during cleanup Kishon Vijay Abraham I 2021-02-22 11:23 ` Kishon Vijay Abraham I 2021-02-22 11:23 ` [PATCH v2 6/9] phy: ti: j721e-wiz: Configure full rate divider for AM64 Kishon Vijay Abraham I 2021-02-22 11:23 ` Kishon Vijay Abraham I 2021-02-22 11:23 ` [PATCH v2 7/9] phy: ti: j721e-wiz: Model the internal clocks without device tree input Kishon Vijay Abraham I 2021-02-22 11:23 ` Kishon Vijay Abraham I 2021-02-22 11:23 ` [PATCH v2 8/9] phy: ti: j721e-wiz: Enable reference clock output in cmn_refclk_<p/m> Kishon Vijay Abraham I 2021-02-22 11:23 ` Kishon Vijay Abraham I 2021-02-22 11:23 ` [PATCH v2 9/9] phy: cadence-torrent: Add support to drive refclk out Kishon Vijay Abraham I 2021-02-22 11:23 ` Kishon Vijay Abraham I 2021-02-22 19:45 ` kernel test robot 2021-02-22 19:45 ` kernel test robot 2021-02-22 19:45 ` kernel test robot 2021-03-09 14:21 ` Swapnil Kashinath Jakhade 2021-03-09 14:21 ` Swapnil Kashinath Jakhade 2021-03-10 10:24 ` Kishon Vijay Abraham I 2021-03-10 10:24 ` Kishon Vijay Abraham I
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