* FAILED: patch "[PATCH] drm/amd/pm: add GFXCLK/SCLK clocks level print support for" failed to apply to 5.15-stable tree
@ 2021-11-23 11:55 gregkh
2021-11-24 2:36 ` Yuan, Perry
0 siblings, 1 reply; 2+ messages in thread
From: gregkh @ 2021-11-23 11:55 UTC (permalink / raw)
To: Perry.Yuan, Ray.Huang, alexander.deucher; +Cc: stable
The patch below does not apply to the 5.15-stable tree.
If someone wants it applied there, or to any other stable or longterm
tree, then please email the backport, including the original git commit
id to <stable@vger.kernel.org>.
thanks,
greg k-h
------------------ original commit in Linus's tree ------------------
From 3dac776e349a214c07fb2b0e5973947b0aade4f6 Mon Sep 17 00:00:00 2001
From: Perry Yuan <Perry.Yuan@amd.com>
Date: Thu, 28 Oct 2021 06:05:42 -0400
Subject: [PATCH] drm/amd/pm: add GFXCLK/SCLK clocks level print support for
APUs
add support that allow the userspace tool like RGP to get the GFX clock
value at runtime, the fix follow the old way to show the min/current/max
clocks level for compatible consideration.
=== Test ===
$ cat /sys/class/drm/card0/device/pp_dpm_sclk
0: 200Mhz *
1: 1100Mhz
2: 1600Mhz
then run stress test on one APU system.
$ cat /sys/class/drm/card0/device/pp_dpm_sclk
0: 200Mhz
1: 1040Mhz *
2: 1600Mhz
The current GFXCLK value is updated at runtime.
BugLink: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5260
Reviewed-by: Huang Ray <Ray.Huang@amd.com>
Signed-off-by: Perry Yuan <Perry.Yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
index cbc3f99e8573..2238ee19c222 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
@@ -309,6 +309,7 @@ static int cyan_skillfish_print_clk_levels(struct smu_context *smu,
{
int ret = 0, size = 0;
uint32_t cur_value = 0;
+ int i;
smu_cmn_get_sysfs_buf(&buf, &size);
@@ -334,8 +335,6 @@ static int cyan_skillfish_print_clk_levels(struct smu_context *smu,
size += sysfs_emit_at(buf, size, "VDDC: %7umV %10umV\n",
CYAN_SKILLFISH_VDDC_MIN, CYAN_SKILLFISH_VDDC_MAX);
break;
- case SMU_GFXCLK:
- case SMU_SCLK:
case SMU_FCLK:
case SMU_MCLK:
case SMU_SOCCLK:
@@ -346,6 +345,25 @@ static int cyan_skillfish_print_clk_levels(struct smu_context *smu,
return ret;
size += sysfs_emit_at(buf, size, "0: %uMhz *\n", cur_value);
break;
+ case SMU_SCLK:
+ case SMU_GFXCLK:
+ ret = cyan_skillfish_get_current_clk_freq(smu, clk_type, &cur_value);
+ if (ret)
+ return ret;
+ if (cur_value == CYAN_SKILLFISH_SCLK_MAX)
+ i = 2;
+ else if (cur_value == CYAN_SKILLFISH_SCLK_MIN)
+ i = 0;
+ else
+ i = 1;
+ size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", CYAN_SKILLFISH_SCLK_MIN,
+ i == 0 ? "*" : "");
+ size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
+ i == 1 ? cur_value : cyan_skillfish_sclk_default,
+ i == 1 ? "*" : "");
+ size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", CYAN_SKILLFISH_SCLK_MAX,
+ i == 2 ? "*" : "");
+ break;
default:
dev_warn(smu->adev->dev, "Unsupported clock type\n");
return ret;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index 421f38e8dada..c02ed65ffa38 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -683,6 +683,7 @@ static int vangogh_print_clk_levels(struct smu_context *smu,
int i, size = 0, ret = 0;
uint32_t cur_value = 0, value = 0, count = 0;
bool cur_value_match_level = false;
+ uint32_t min, max;
memset(&metrics, 0, sizeof(metrics));
@@ -743,6 +744,13 @@ static int vangogh_print_clk_levels(struct smu_context *smu,
if (ret)
return ret;
break;
+ case SMU_GFXCLK:
+ case SMU_SCLK:
+ ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetGfxclkFrequency, 0, &cur_value);
+ if (ret) {
+ return ret;
+ }
+ break;
default:
break;
}
@@ -768,6 +776,24 @@ static int vangogh_print_clk_levels(struct smu_context *smu,
if (!cur_value_match_level)
size += sysfs_emit_at(buf, size, " %uMhz *\n", cur_value);
break;
+ case SMU_GFXCLK:
+ case SMU_SCLK:
+ min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
+ max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
+ if (cur_value == max)
+ i = 2;
+ else if (cur_value == min)
+ i = 0;
+ else
+ i = 1;
+ size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min,
+ i == 0 ? "*" : "");
+ size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
+ i == 1 ? cur_value : VANGOGH_UMD_PSTATE_STANDARD_GFXCLK,
+ i == 1 ? "*" : "");
+ size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max,
+ i == 2 ? "*" : "");
+ break;
default:
break;
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
index 8215bbf5ed7c..caf1775d48ef 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
@@ -697,6 +697,11 @@ static int yellow_carp_get_current_clk_freq(struct smu_context *smu,
case SMU_FCLK:
return smu_cmn_send_smc_msg_with_param(smu,
SMU_MSG_GetFclkFrequency, 0, value);
+ case SMU_GFXCLK:
+ case SMU_SCLK:
+ return smu_cmn_send_smc_msg_with_param(smu,
+ SMU_MSG_GetGfxclkFrequency, 0, value);
+ break;
default:
return -EINVAL;
}
@@ -967,6 +972,7 @@ static int yellow_carp_print_clk_levels(struct smu_context *smu,
{
int i, size = 0, ret = 0;
uint32_t cur_value = 0, value = 0, count = 0;
+ uint32_t min, max;
smu_cmn_get_sysfs_buf(&buf, &size);
@@ -1005,6 +1011,27 @@ static int yellow_carp_print_clk_levels(struct smu_context *smu,
cur_value == value ? "*" : "");
}
break;
+ case SMU_GFXCLK:
+ case SMU_SCLK:
+ ret = yellow_carp_get_current_clk_freq(smu, clk_type, &cur_value);
+ if (ret)
+ goto print_clk_out;
+ min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
+ max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
+ if (cur_value == max)
+ i = 2;
+ else if (cur_value == min)
+ i = 0;
+ else
+ i = 1;
+ size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min,
+ i == 0 ? "*" : "");
+ size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
+ i == 1 ? cur_value : YELLOW_CARP_UMD_PSTATE_GFXCLK,
+ i == 1 ? "*" : "");
+ size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max,
+ i == 2 ? "*" : "");
+ break;
default:
break;
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.h
index b3ad8352c68a..a9205a8ea3ad 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.h
@@ -24,5 +24,6 @@
#define __YELLOW_CARP_PPT_H__
extern void yellow_carp_set_ppt_funcs(struct smu_context *smu);
+#define YELLOW_CARP_UMD_PSTATE_GFXCLK 1100
#endif
^ permalink raw reply related [flat|nested] 2+ messages in thread
* RE: FAILED: patch "[PATCH] drm/amd/pm: add GFXCLK/SCLK clocks level print support for" failed to apply to 5.15-stable tree
2021-11-23 11:55 FAILED: patch "[PATCH] drm/amd/pm: add GFXCLK/SCLK clocks level print support for" failed to apply to 5.15-stable tree gregkh
@ 2021-11-24 2:36 ` Yuan, Perry
0 siblings, 0 replies; 2+ messages in thread
From: Yuan, Perry @ 2021-11-24 2:36 UTC (permalink / raw)
To: gregkh, Huang, Ray, Deucher, Alexander; +Cc: stable
[AMD Official Use Only]
Hi Greg.
Thanks for your reminder.
I will check the failure with my team for the 5.15 stable tree.
Perry.
> -----Original Message-----
> From: gregkh@linuxfoundation.org <gregkh@linuxfoundation.org>
> Sent: Tuesday, November 23, 2021 7:55 PM
> To: Yuan, Perry <Perry.Yuan@amd.com>; Huang, Ray
> <Ray.Huang@amd.com>; Deucher, Alexander
> <Alexander.Deucher@amd.com>
> Cc: stable@vger.kernel.org
> Subject: FAILED: patch "[PATCH] drm/amd/pm: add GFXCLK/SCLK clocks level
> print support for" failed to apply to 5.15-stable tree
>
> [CAUTION: External Email]
>
> The patch below does not apply to the 5.15-stable tree.
> If someone wants it applied there, or to any other stable or longterm tree,
> then please email the backport, including the original git commit id to
> <stable@vger.kernel.org>.
>
> thanks,
>
> greg k-h
>
> ------------------ original commit in Linus's tree ------------------
>
> From 3dac776e349a214c07fb2b0e5973947b0aade4f6 Mon Sep 17 00:00:00
> 2001
> From: Perry Yuan <Perry.Yuan@amd.com>
> Date: Thu, 28 Oct 2021 06:05:42 -0400
> Subject: [PATCH] drm/amd/pm: add GFXCLK/SCLK clocks level print support
> for APUs
>
> add support that allow the userspace tool like RGP to get the GFX clock value
> at runtime, the fix follow the old way to show the min/current/max clocks
> level for compatible consideration.
>
> === Test ===
> $ cat /sys/class/drm/card0/device/pp_dpm_sclk
> 0: 200Mhz *
> 1: 1100Mhz
> 2: 1600Mhz
>
> then run stress test on one APU system.
> $ cat /sys/class/drm/card0/device/pp_dpm_sclk
> 0: 200Mhz
> 1: 1040Mhz *
> 2: 1600Mhz
>
> The current GFXCLK value is updated at runtime.
>
> BugLink:
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitla
> b.freedesktop.org%2Fmesa%2Fmesa%2F-
> %2Fissues%2F5260&data=04%7C01%7CPerry.Yuan%40amd.com%7C3d
> 58c619845a45ed214908d9ae782402%7C3dd8961fe4884e608e11a82d994e18
> 3d%7C0%7C0%7C637732653292775514%7CUnknown%7CTWFpbGZsb3d8eyJ
> WIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%
> 7C3000&sdata=dA2FL16ep6Pchu%2BN6d7GgHl6NzolgEwaY4zCUnUuB6
> A%3D&reserved=0
> Reviewed-by: Huang Ray <Ray.Huang@amd.com>
> Signed-off-by: Perry Yuan <Perry.Yuan@amd.com>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> Cc: stable@vger.kernel.org
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
> index cbc3f99e8573..2238ee19c222 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
> @@ -309,6 +309,7 @@ static int cyan_skillfish_print_clk_levels(struct
> smu_context *smu, {
> int ret = 0, size = 0;
> uint32_t cur_value = 0;
> + int i;
>
> smu_cmn_get_sysfs_buf(&buf, &size);
>
> @@ -334,8 +335,6 @@ static int cyan_skillfish_print_clk_levels(struct
> smu_context *smu,
> size += sysfs_emit_at(buf, size, "VDDC: %7umV %10umV\n",
> CYAN_SKILLFISH_VDDC_MIN,
> CYAN_SKILLFISH_VDDC_MAX);
> break;
> - case SMU_GFXCLK:
> - case SMU_SCLK:
> case SMU_FCLK:
> case SMU_MCLK:
> case SMU_SOCCLK:
> @@ -346,6 +345,25 @@ static int cyan_skillfish_print_clk_levels(struct
> smu_context *smu,
> return ret;
> size += sysfs_emit_at(buf, size, "0: %uMhz *\n", cur_value);
> break;
> + case SMU_SCLK:
> + case SMU_GFXCLK:
> + ret = cyan_skillfish_get_current_clk_freq(smu, clk_type,
> &cur_value);
> + if (ret)
> + return ret;
> + if (cur_value == CYAN_SKILLFISH_SCLK_MAX)
> + i = 2;
> + else if (cur_value == CYAN_SKILLFISH_SCLK_MIN)
> + i = 0;
> + else
> + i = 1;
> + size += sysfs_emit_at(buf, size, "0: %uMhz %s\n",
> CYAN_SKILLFISH_SCLK_MIN,
> + i == 0 ? "*" : "");
> + size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
> + i == 1 ? cur_value : cyan_skillfish_sclk_default,
> + i == 1 ? "*" : "");
> + size += sysfs_emit_at(buf, size, "2: %uMhz %s\n",
> CYAN_SKILLFISH_SCLK_MAX,
> + i == 2 ? "*" : "");
> + break;
> default:
> dev_warn(smu->adev->dev, "Unsupported clock type\n");
> return ret;
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> index 421f38e8dada..c02ed65ffa38 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> @@ -683,6 +683,7 @@ static int vangogh_print_clk_levels(struct
> smu_context *smu,
> int i, size = 0, ret = 0;
> uint32_t cur_value = 0, value = 0, count = 0;
> bool cur_value_match_level = false;
> + uint32_t min, max;
>
> memset(&metrics, 0, sizeof(metrics));
>
> @@ -743,6 +744,13 @@ static int vangogh_print_clk_levels(struct
> smu_context *smu,
> if (ret)
> return ret;
> break;
> + case SMU_GFXCLK:
> + case SMU_SCLK:
> + ret = smu_cmn_send_smc_msg_with_param(smu,
> SMU_MSG_GetGfxclkFrequency, 0, &cur_value);
> + if (ret) {
> + return ret;
> + }
> + break;
> default:
> break;
> }
> @@ -768,6 +776,24 @@ static int vangogh_print_clk_levels(struct
> smu_context *smu,
> if (!cur_value_match_level)
> size += sysfs_emit_at(buf, size, " %uMhz *\n", cur_value);
> break;
> + case SMU_GFXCLK:
> + case SMU_SCLK:
> + min = (smu->gfx_actual_hard_min_freq > 0) ? smu-
> >gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
> + max = (smu->gfx_actual_soft_max_freq > 0) ? smu-
> >gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
> + if (cur_value == max)
> + i = 2;
> + else if (cur_value == min)
> + i = 0;
> + else
> + i = 1;
> + size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min,
> + i == 0 ? "*" : "");
> + size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
> + i == 1 ? cur_value :
> VANGOGH_UMD_PSTATE_STANDARD_GFXCLK,
> + i == 1 ? "*" : "");
> + size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max,
> + i == 2 ? "*" : "");
> + break;
> default:
> break;
> }
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> index 8215bbf5ed7c..caf1775d48ef 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> @@ -697,6 +697,11 @@ static int yellow_carp_get_current_clk_freq(struct
> smu_context *smu,
> case SMU_FCLK:
> return smu_cmn_send_smc_msg_with_param(smu,
> SMU_MSG_GetFclkFrequency, 0, value);
> + case SMU_GFXCLK:
> + case SMU_SCLK:
> + return smu_cmn_send_smc_msg_with_param(smu,
> + SMU_MSG_GetGfxclkFrequency, 0, value);
> + break;
> default:
> return -EINVAL;
> }
> @@ -967,6 +972,7 @@ static int yellow_carp_print_clk_levels(struct
> smu_context *smu, {
> int i, size = 0, ret = 0;
> uint32_t cur_value = 0, value = 0, count = 0;
> + uint32_t min, max;
>
> smu_cmn_get_sysfs_buf(&buf, &size);
>
> @@ -1005,6 +1011,27 @@ static int yellow_carp_print_clk_levels(struct
> smu_context *smu,
> cur_value == value ? "*" : "");
> }
> break;
> + case SMU_GFXCLK:
> + case SMU_SCLK:
> + ret = yellow_carp_get_current_clk_freq(smu, clk_type,
> &cur_value);
> + if (ret)
> + goto print_clk_out;
> + min = (smu->gfx_actual_hard_min_freq > 0) ? smu-
> >gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
> + max = (smu->gfx_actual_soft_max_freq > 0) ? smu-
> >gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
> + if (cur_value == max)
> + i = 2;
> + else if (cur_value == min)
> + i = 0;
> + else
> + i = 1;
> + size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min,
> + i == 0 ? "*" : "");
> + size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
> + i == 1 ? cur_value : YELLOW_CARP_UMD_PSTATE_GFXCLK,
> + i == 1 ? "*" : "");
> + size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max,
> + i == 2 ? "*" : "");
> + break;
> default:
> break;
> }
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.h
> b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.h
> index b3ad8352c68a..a9205a8ea3ad 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.h
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.h
> @@ -24,5 +24,6 @@
> #define __YELLOW_CARP_PPT_H__
>
> extern void yellow_carp_set_ppt_funcs(struct smu_context *smu);
> +#define YELLOW_CARP_UMD_PSTATE_GFXCLK 1100
>
> #endif
^ permalink raw reply [flat|nested] 2+ messages in thread
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2021-11-23 11:55 FAILED: patch "[PATCH] drm/amd/pm: add GFXCLK/SCLK clocks level print support for" failed to apply to 5.15-stable tree gregkh
2021-11-24 2:36 ` Yuan, Perry
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