From: "Shaikh, Azhar" <azhar.shaikh-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
To: Jarkko Sakkinen
<jarkko.sakkinen-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>,
"jgunthorpe-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org"
<jgunthorpe-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>,
"tpmdd-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org"
<tpmdd-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org>,
"linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
<linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
Cc: "linux-security-module-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
<linux-security-module-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
Subject: Re: [PATCH v4] tpm: Enable CLKRUN protocol for Braswell systems
Date: Mon, 19 Jun 2017 02:12:44 +0000 [thread overview]
Message-ID: <5FFFAD06ADE1CA4381B3F0F7C6AF5828914FBD@ORSMSX109.amr.corp.intel.com> (raw)
In-Reply-To: <1497829956.2552.10.camel-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
> -----Original Message-----
> From: Jarkko Sakkinen [mailto:jarkko.sakkinen-VuQAYsv1563Yd54FQh9/CA@public.gmane.org]
> Sent: Sunday, June 18, 2017 4:53 PM
> To: Shaikh, Azhar <azhar.shaikh-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>;
> jgunthorpe-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org; tpmdd-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org;
> linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: linux-security-module-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Subject: Re: [PATCH v4] tpm: Enable CLKRUN protocol for Braswell systems
>
> On Wed, 2017-06-14 at 12:39 -0700, Azhar Shaikh wrote:
> > To overcome a hardware limitation on Intel Braswell systems, disable
> > CLKRUN protocol during TPM transactions and re-enable once the
> > transaction is completed.
> >
> > Signed-off-by: Azhar Shaikh <azhar.shaikh-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
>
> Does not merge to my tree:
>
> git://git.infradead.org/users/jjs/linux-tpmdd.git
>
> Please fix.
>
Sure will rebase and send again.
> /Jarkko
>
> > ---
> > Changes from v1:
> > - Add CONFIG_X86 around disable_lpc_clk_run() and enable_lpc_clk_run()
> > to avoid
> > - build breakage on architectures which do not implement
> > kmap_atomic_pfn()
> >
> > Changes from v2:
> > - Use ioremap()/iounmap() instead of
> kmap_atomic_pfn()/kunmap_atomic()
> > - Move is_bsw() and all macros from tpm.h to tpm_tis.c file.
> > - Add the is_bsw() check in disable_lpc_clk_run() and
> > enable_lpc_clk_run()
> > - instead of adding it in each read/write API.
> >
> > Changes from v3:
> > - Move the code under #ifdef CONFIG_X86 and create stub functions for
> > everything else
> > - Rename the functions disable_lpc_clk_run() ->
> > tpm_platform_begin_xfer() and
> > - enable_lpc_clk_run() -> tpm_platform_end_xfer()
> > - Remove wmb()
> > - Correct the parameters for outb()
> >
> > drivers/char/tpm/tpm.h | 4 ++
> > drivers/char/tpm/tpm_tis.c | 112
> > +++++++++++++++++++++++++++++++++++++++++++++
> > 2 files changed, 116 insertions(+)
> >
> > diff --git a/drivers/char/tpm/tpm.h b/drivers/char/tpm/tpm.h index
> > 4b4c8dee3096..6b769fbc4407 100644
> > --- a/drivers/char/tpm/tpm.h
> > +++ b/drivers/char/tpm/tpm.h
> > @@ -36,6 +36,10 @@
> > #include <linux/highmem.h>
> > #include <crypto/hash_info.h>
> >
> > +#ifdef CONFIG_X86
> > +#include <asm/intel-family.h>
> > +#endif
> > +
> > enum tpm_const {
> > TPM_MINOR = 224, /* officially assigned */
> > TPM_BUFSIZE = 4096,
> > diff --git a/drivers/char/tpm/tpm_tis.c b/drivers/char/tpm/tpm_tis.c
> > index c7e1384f1b08..ce6f1a8b0510 100644
> > --- a/drivers/char/tpm/tpm_tis.c
> > +++ b/drivers/char/tpm/tpm_tis.c
> > @@ -89,13 +89,93 @@ static inline int is_itpm(struct acpi_device *dev)
> > } #endif
> >
> > +#ifdef CONFIG_X86
> > +#define INTEL_LEGACY_BLK_BASE_ADDR 0xFED08000
> > +#define ILB_REMAP_SIZE 0x100
> > +#define LPC_CNTRL_REG_OFFSET 0x84
> > +#define LPC_CLKRUN_EN (1 << 2)
> > +
> > +void __iomem *ilb_base_addr;
> > +
> > +static inline bool is_bsw(void)
> > +{
> > + return ((boot_cpu_data.x86_model ==
> INTEL_FAM6_ATOM_AIRMONT) ? 1 :
> > +0); }
> > +
> > +/**
> > + * tpm_platform_begin_xfer() - clear LPC CLKRUN_EN i.e. clocks will
> > +be running */ static void tpm_platform_begin_xfer(void) {
> > + u32 clkrun_val;
> > +
> > + if (!is_bsw())
> > + return;
> > +
> > + clkrun_val = ioread32(ilb_base_addr + LPC_CNTRL_REG_OFFSET);
> > +
> > + /* Disable LPC CLKRUN# */
> > + clkrun_val &= ~LPC_CLKRUN_EN;
> > + iowrite32(clkrun_val, ilb_base_addr + LPC_CNTRL_REG_OFFSET);
> > +
> > + /*
> > + * Write any random value on port 0x80 which is on LPC, to make
> > + * sure LPC clock is running before sending any TPM command.
> > + */
> > + outb(0xCC, 0x80);
> > +
> > +}
> > +
> > +/**
> > + * tpm_platform_end_xfer() - set LPC CLKRUN_EN i.e. clocks can be
> > +turned off */ static void tpm_platform_end_xfer(void) {
> > + u32 clkrun_val;
> > +
> > + if (!is_bsw())
> > + return;
> > +
> > + clkrun_val = ioread32(ilb_base_addr + LPC_CNTRL_REG_OFFSET);
> > +
> > + /* Enable LPC CLKRUN# */
> > + clkrun_val |= LPC_CLKRUN_EN;
> > + iowrite32(clkrun_val, ilb_base_addr + LPC_CNTRL_REG_OFFSET);
> > +
> > + /*
> > + * Write any random value on port 0x80 which is on LPC, to make
> > + * sure LPC clock is running before sending any TPM command.
> > + */
> > + outb(0xCC, 0x80);
> > +
> > +}
> > +#else
> > +static inline bool is_bsw(void)
> > +{
> > + return false;
> > +}
> > +
> > +static void tpm_platform_begin_xfer(void) { }
> > +
> > +static void tpm_platform_end_xfer(void) { } #endif
> > +
> > static int tpm_tcg_read_bytes(struct tpm_tis_data *data, u32 addr, u16
> len,
> > u8 *result)
> > {
> > struct tpm_tis_tcg_phy *phy = to_tpm_tis_tcg_phy(data);
> >
> > + tpm_platform_begin_xfer();
> > +
> > while (len--)
> > *result++ = ioread8(phy->iobase + addr);
> > +
> > + tpm_platform_end_xfer();
> > +
> > return 0;
> > }
> >
> > @@ -104,8 +184,13 @@ static int tpm_tcg_write_bytes(struct
> > tpm_tis_data *data, u32 addr, u16 len, {
> > struct tpm_tis_tcg_phy *phy = to_tpm_tis_tcg_phy(data);
> >
> > + tpm_platform_begin_xfer();
> > +
> > while (len--)
> > iowrite8(*value++, phy->iobase + addr);
> > +
> > + tpm_platform_end_xfer();
> > +
> > return 0;
> > }
> >
> > @@ -113,7 +198,12 @@ static int tpm_tcg_read16(struct tpm_tis_data
> > *data, u32 addr, u16 *result) {
> > struct tpm_tis_tcg_phy *phy = to_tpm_tis_tcg_phy(data);
> >
> > + tpm_platform_begin_xfer();
> > +
> > *result = ioread16(phy->iobase + addr);
> > +
> > + tpm_platform_end_xfer();
> > +
> > return 0;
> > }
> >
> > @@ -121,7 +211,12 @@ static int tpm_tcg_read32(struct tpm_tis_data
> > *data, u32 addr, u32 *result) {
> > struct tpm_tis_tcg_phy *phy = to_tpm_tis_tcg_phy(data);
> >
> > + tpm_platform_begin_xfer();
> > +
> > *result = ioread32(phy->iobase + addr);
> > +
> > + tpm_platform_end_xfer();
> > +
> > return 0;
> > }
> >
> > @@ -129,7 +224,12 @@ static int tpm_tcg_write32(struct tpm_tis_data
> > *data, u32 addr, u32 value) {
> > struct tpm_tis_tcg_phy *phy = to_tpm_tis_tcg_phy(data);
> >
> > + tpm_platform_begin_xfer();
> > +
> > iowrite32(value, phy->iobase + addr);
> > +
> > + tpm_platform_end_xfer();
> > +
> > return 0;
> > }
> >
> > @@ -191,6 +291,12 @@ static int tpm_tis_pnp_init(struct pnp_dev
> *pnp_dev,
> > acpi_dev_handle = ACPI_HANDLE(&pnp_dev->dev);
> > }
> >
> > +#ifdef CONFIG_X86
> > + if (is_bsw())
> > + ilb_base_addr = ioremap(INTEL_LEGACY_BLK_BASE_ADDR,
> > + ILB_REMAP_SIZE);
> > +#endif
> > +
> > return tpm_tis_init(&pnp_dev->dev, &tpm_info, acpi_dev_handle);
> }
> >
> > @@ -214,6 +320,12 @@ static void tpm_tis_pnp_remove(struct pnp_dev
> > *dev)
> >
> > tpm_chip_unregister(chip);
> > tpm_tis_remove(chip);
> > +
> > +#ifdef CONFIG_X86
> > + if (is_bsw())
> > + iounmap(ilb_base_addr);
> > +#endif
> > +
> > }
> >
> > static struct pnp_driver tis_pnp_driver = {
------------------------------------------------------------------------------
Check out the vibrant tech community on one of the world's most
engaging tech sites, Slashdot.org! http://sdm.link/slashdot
next prev parent reply other threads:[~2017-06-19 2:12 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-01 19:13 [PATCH] tpm: Enable CLKRUN protocol for Braswell systems Azhar Shaikh
2017-06-01 23:56 ` kbuild test robot
2017-06-02 2:04 ` [PATCH v2] " Azhar Shaikh
[not found] ` <1496369044-38234-1-git-send-email-azhar.shaikh-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
2017-06-05 13:32 ` Jarkko Sakkinen
2017-06-05 18:42 ` Shaikh, Azhar
2017-06-06 17:13 ` Jarkko Sakkinen
2017-06-07 21:23 ` [PATCH v3] " Azhar Shaikh
2017-06-07 21:44 ` Alan Cox
2017-06-08 1:11 ` Shaikh, Azhar
2017-06-08 12:38 ` Jarkko Sakkinen
2017-06-08 18:22 ` Alan Cox
2017-06-08 18:39 ` Jason Gunthorpe
2017-06-08 18:50 ` Alan Cox
2017-06-08 19:27 ` Shaikh, Azhar
2017-06-10 11:06 ` Jarkko Sakkinen
2017-06-08 19:02 ` Shaikh, Azhar
2017-06-08 23:46 ` [PATCH v4] " Azhar Shaikh
2017-06-10 11:13 ` Jarkko Sakkinen
2017-06-10 16:35 ` Shaikh, Azhar
2017-06-12 7:50 ` Jarkko Sakkinen
2017-06-14 0:51 ` Shaikh, Azhar
2017-06-14 14:46 ` Jarkko Sakkinen
2017-06-14 17:17 ` Shaikh, Azhar
2017-06-14 19:39 ` Azhar Shaikh
2017-06-18 23:52 ` Jarkko Sakkinen
[not found] ` <1497829956.2552.10.camel-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
2017-06-19 2:12 ` Shaikh, Azhar [this message]
2017-06-19 2:17 ` [PATCH v5] " Azhar Shaikh
2017-06-19 14:51 ` Jarkko Sakkinen
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=5FFFAD06ADE1CA4381B3F0F7C6AF5828914FBD@ORSMSX109.amr.corp.intel.com \
--to=azhar.shaikh-ral2jqcrhueavxtiumwx3w@public.gmane.org \
--cc=jarkko.sakkinen-VuQAYsv1563Yd54FQh9/CA@public.gmane.org \
--cc=jgunthorpe-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org \
--cc=linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org \
--cc=linux-security-module-u79uwXL29TY76Z2rM5mHXA@public.gmane.org \
--cc=tpmdd-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).