* [PATCH v2 1/4] riscv: t-head: licheepi4a: initial support added
2023-07-08 11:24 [PATCH v2 0/4] riscv: Initial support for Lichee PI 4A board Yixun Lan
@ 2023-07-08 11:24 ` Yixun Lan
2023-07-08 11:24 ` [PATCH v2 2/4] riscv: dts: t-head: Add basic device tree for Sipeed Lichee PI 4A board Yixun Lan
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Yixun Lan @ 2023-07-08 11:24 UTC (permalink / raw)
To: u-boot; +Cc: Rick Chen, Leo, Wei Fu, Yixun Lan, Jisheng Zhang, Guo Ren
Add support for Sipeed's Lichee Pi 4A board which based on T-HEAD's
TH1520 SoC, only minimal device tree and serial console are enabled,
so it's capable of chain booting from T-HEAD's vendor u-boot.
Reviewed-by: Wei Fu <wefu@redhat.com>
Signed-off-by: Yixun Lan <dlan@gentoo.org>
---
arch/riscv/Kconfig | 5 ++++
board/thead/th1520_lpi4a/Kconfig | 42 ++++++++++++++++++++++++++++
board/thead/th1520_lpi4a/MAINTAINERS | 7 +++++
board/thead/th1520_lpi4a/Makefile | 5 ++++
board/thead/th1520_lpi4a/board.c | 15 ++++++++++
include/configs/th1520_lpi4a.h | 22 +++++++++++++++
6 files changed, 96 insertions(+)
create mode 100644 board/thead/th1520_lpi4a/Kconfig
create mode 100644 board/thead/th1520_lpi4a/MAINTAINERS
create mode 100644 board/thead/th1520_lpi4a/Makefile
create mode 100644 board/thead/th1520_lpi4a/board.c
create mode 100644 include/configs/th1520_lpi4a.h
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index f6ed05906a..419b6171a9 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -27,6 +27,10 @@ config TARGET_SIFIVE_UNMATCHED
config TARGET_STARFIVE_VISIONFIVE2
bool "Support StarFive VisionFive2 Board"
+config TARGET_TH1520_LPI4A
+ bool "Support Sipeed's TH1520 Lichee PI 4A Board"
+ select SYS_CACHE_SHIFT_6
+
config TARGET_SIPEED_MAIX
bool "Support Sipeed Maix Board"
select SYS_CACHE_SHIFT_6
@@ -66,6 +70,7 @@ source "board/emulation/qemu-riscv/Kconfig"
source "board/microchip/mpfs_icicle/Kconfig"
source "board/sifive/unleashed/Kconfig"
source "board/sifive/unmatched/Kconfig"
+source "board/thead/th1520_lpi4a/Kconfig"
source "board/openpiton/riscv64/Kconfig"
source "board/sipeed/maix/Kconfig"
source "board/starfive/visionfive2/Kconfig"
diff --git a/board/thead/th1520_lpi4a/Kconfig b/board/thead/th1520_lpi4a/Kconfig
new file mode 100644
index 0000000000..622246127c
--- /dev/null
+++ b/board/thead/th1520_lpi4a/Kconfig
@@ -0,0 +1,42 @@
+if TARGET_TH1520_LPI4A
+
+config ARCH_THEAD
+ bool
+ default y
+
+config SYS_BOARD
+ default "th1520_lpi4a"
+
+config SYS_VENDOR
+ default "thead"
+
+config SYS_CPU
+ default "generic"
+
+config SYS_CONFIG_NAME
+ default "th1520_lpi4a"
+
+config TEXT_BASE
+ default 0x01b00000 if SPL
+ default 0x01c00000 if !RISCV_SMODE
+ default 0x01c00000 if RISCV_SMODE
+
+config SPL_TEXT_BASE
+ default 0x08000000
+
+config SPL_OPENSBI_LOAD_ADDR
+ default 0x80000000
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select ARCH_EARLY_INIT_R
+ imply CPU
+ imply CPU_RISCV
+ imply RISCV_TIMER if RISCV_SMODE
+ imply CMD_CPU
+ imply SMP
+ imply SUPPORT_OF_CONTROL
+ imply OF_CONTROL
+ imply OF_REAL
+
+endif
diff --git a/board/thead/th1520_lpi4a/MAINTAINERS b/board/thead/th1520_lpi4a/MAINTAINERS
new file mode 100644
index 0000000000..36c7ab7cc3
--- /dev/null
+++ b/board/thead/th1520_lpi4a/MAINTAINERS
@@ -0,0 +1,7 @@
+Lichee PI 4A
+M: Wei Fu <wefu@redhat.com>
+M: Yixun Lan <dlan@gentoo.org>
+S: Maintained
+F: board/thead/th1520_lpi4a/
+F: configs/th1520_lpi4a_defconfig
+F: doc/board/thead/lpi4a.rst
diff --git a/board/thead/th1520_lpi4a/Makefile b/board/thead/th1520_lpi4a/Makefile
new file mode 100644
index 0000000000..9671b3bbb0
--- /dev/null
+++ b/board/thead/th1520_lpi4a/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2023, Yixun Lan <dlan@gentoo.org>
+
+obj-y += board.o
diff --git a/board/thead/th1520_lpi4a/board.c b/board/thead/th1520_lpi4a/board.c
new file mode 100644
index 0000000000..16c3e456b3
--- /dev/null
+++ b/board/thead/th1520_lpi4a/board.c
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2023, Yixun Lan <dlan@gentoo.org>
+ *
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+
+int board_init(void)
+{
+ enable_caches();
+
+ return 0;
+}
diff --git a/include/configs/th1520_lpi4a.h b/include/configs/th1520_lpi4a.h
new file mode 100644
index 0000000000..87496a52c4
--- /dev/null
+++ b/include/configs/th1520_lpi4a.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2023 Yixun Lan <dlan@gentoo.org>
+ *
+ */
+
+#ifndef __TH1520_LPI4A_H
+#define __TH1520_LPI4A_H
+
+#include <linux/sizes.h>
+
+#define CFG_SYS_SDRAM_BASE 0x00000000
+
+#define UART_BASE 0xffe7014000
+#define UART_REG_WIDTH 32
+
+/* Environment options */
+
+#define CFG_EXTRA_ENV_SETTINGS \
+ "PS1=[LPi4A]# \0"
+
+#endif /* __TH1520_LPI4A_H */
--
2.39.3
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 2/4] riscv: dts: t-head: Add basic device tree for Sipeed Lichee PI 4A board
2023-07-08 11:24 [PATCH v2 0/4] riscv: Initial support for Lichee PI 4A board Yixun Lan
2023-07-08 11:24 ` [PATCH v2 1/4] riscv: t-head: licheepi4a: initial support added Yixun Lan
@ 2023-07-08 11:24 ` Yixun Lan
2023-07-08 11:24 ` [PATCH v2 3/4] configs: th1520_lpi4a_defconfig: Add initial config Yixun Lan
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Yixun Lan @ 2023-07-08 11:24 UTC (permalink / raw)
To: u-boot; +Cc: Rick Chen, Leo, Wei Fu, Yixun Lan, Jisheng Zhang, Guo Ren
Only add basic support for CPU, PLIC UART and Timer.
Reviewed-by: Wei Fu <wefu@redhat.com>
Signed-off-by: Yixun Lan <dlan@gentoo.org>
---
arch/riscv/dts/Makefile | 1 +
arch/riscv/dts/th1520-lichee-module-4a.dtsi | 34 ++
arch/riscv/dts/th1520-lichee-pi-4a.dts | 32 ++
arch/riscv/dts/th1520.dtsi | 406 ++++++++++++++++++++
4 files changed, 473 insertions(+)
create mode 100644 arch/riscv/dts/th1520-lichee-module-4a.dtsi
create mode 100644 arch/riscv/dts/th1520-lichee-pi-4a.dts
create mode 100644 arch/riscv/dts/th1520.dtsi
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 79a58694f5..72fd815a40 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -9,6 +9,7 @@ dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2-v1.3b.dtb
dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2-v1.2a.dtb
+dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb
include $(srctree)/scripts/Makefile.dts
targets += $(dtb-y)
diff --git a/arch/riscv/dts/th1520-lichee-module-4a.dtsi b/arch/riscv/dts/th1520-lichee-module-4a.dtsi
new file mode 100644
index 0000000000..dc00e3dfa0
--- /dev/null
+++ b/arch/riscv/dts/th1520-lichee-module-4a.dtsi
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
+ */
+
+/dts-v1/;
+
+#include "th1520.dtsi"
+
+/ {
+ model = "Sipeed Lichee Module 4A";
+ compatible = "sipeed,lichee-module-4a", "thead,th1520";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x00000000 0x2 0x00000000>;
+ };
+};
+
+&osc {
+ clock-frequency = <24000000>;
+};
+
+&osc_32k {
+ clock-frequency = <32768>;
+};
+
+&apb_clk {
+ clock-frequency = <62500000>;
+};
+
+&uart_sclk {
+ clock-frequency = <100000000>;
+};
diff --git a/arch/riscv/dts/th1520-lichee-pi-4a.dts b/arch/riscv/dts/th1520-lichee-pi-4a.dts
new file mode 100644
index 0000000000..a1248b2ee3
--- /dev/null
+++ b/arch/riscv/dts/th1520-lichee-pi-4a.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
+ */
+
+#include "th1520-lichee-module-4a.dtsi"
+
+/ {
+ model = "Sipeed Lichee Pi 4A";
+ compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520";
+
+ aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/riscv/dts/th1520.dtsi b/arch/riscv/dts/th1520.dtsi
new file mode 100644
index 0000000000..f7bfa42243
--- /dev/null
+++ b/arch/riscv/dts/th1520.dtsi
@@ -0,0 +1,406 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Alibaba Group Holding Limited.
+ * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "thead,th1520";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <3000000>;
+
+ c910_0: cpu@0 {
+ compatible = "thead,c910", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ reg = <0>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache>;
+ mmu-type = "riscv,sv39";
+
+ cpu0_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ c910_1: cpu@1 {
+ compatible = "thead,c910", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ reg = <1>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache>;
+ mmu-type = "riscv,sv39";
+
+ cpu1_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ c910_2: cpu@2 {
+ compatible = "thead,c910", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ reg = <2>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache>;
+ mmu-type = "riscv,sv39";
+
+ cpu2_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ c910_3: cpu@3 {
+ compatible = "thead,c910", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ reg = <3>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache>;
+ mmu-type = "riscv,sv39";
+
+ cpu3_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ l2_cache: l2-cache {
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-sets = <1024>;
+ cache-unified;
+ };
+ };
+
+ osc: oscillator {
+ compatible = "fixed-clock";
+ clock-output-names = "osc_24m";
+ #clock-cells = <0>;
+ };
+
+ osc_32k: 32k-oscillator {
+ compatible = "fixed-clock";
+ clock-output-names = "osc_32k";
+ #clock-cells = <0>;
+ };
+
+ apb_clk: apb-clk-clock {
+ compatible = "fixed-clock";
+ clock-output-names = "apb_clk";
+ #clock-cells = <0>;
+ };
+
+ uart_sclk: uart-sclk-clock {
+ compatible = "fixed-clock";
+ clock-output-names = "uart_sclk";
+ #clock-cells = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&plic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ plic: interrupt-controller@ffd8000000 {
+ compatible = "thead,th1520-plic", "thead,c900-plic";
+ reg = <0xff 0xd8000000 0x0 0x01000000>;
+ interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
+ <&cpu1_intc 11>, <&cpu1_intc 9>,
+ <&cpu2_intc 11>, <&cpu2_intc 9>,
+ <&cpu3_intc 11>, <&cpu3_intc 9>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ riscv,ndev = <240>;
+ };
+
+ clint: timer@ffdc000000 {
+ compatible = "thead,th1520-clint", "thead,c900-clint";
+ reg = <0xff 0xdc000000 0x0 0x00010000>;
+ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+ <&cpu1_intc 3>, <&cpu1_intc 7>,
+ <&cpu2_intc 3>, <&cpu2_intc 7>,
+ <&cpu3_intc 3>, <&cpu3_intc 7>;
+ };
+
+ uart0: serial@ffe7014000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0xff 0xe7014000 0x0 0x100>;
+ interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&uart_sclk>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart1: serial@ffe7f00000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0xff 0xe7f00000 0x0 0x100>;
+ interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&uart_sclk>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart3: serial@ffe7f04000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0xff 0xe7f04000 0x0 0x100>;
+ interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&uart_sclk>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ gpio2: gpio@ffe7f34000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xff 0xe7f34000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ portc: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ gpio3: gpio@ffe7f38000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xff 0xe7f38000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ portd: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ gpio0: gpio@ffec005000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xff 0xec005000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ porta: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ gpio1: gpio@ffec006000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xff 0xec006000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ portb: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ uart2: serial@ffec010000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0xff 0xec010000 0x0 0x4000>;
+ interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&uart_sclk>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ timer0: timer@ffefc32000 {
+ compatible = "snps,dw-apb-timer";
+ reg = <0xff 0xefc32000 0x0 0x14>;
+ clocks = <&apb_clk>;
+ clock-names = "timer";
+ interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ timer1: timer@ffefc32014 {
+ compatible = "snps,dw-apb-timer";
+ reg = <0xff 0xefc32014 0x0 0x14>;
+ clocks = <&apb_clk>;
+ clock-names = "timer";
+ interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ timer2: timer@ffefc32028 {
+ compatible = "snps,dw-apb-timer";
+ reg = <0xff 0xefc32028 0x0 0x14>;
+ clocks = <&apb_clk>;
+ clock-names = "timer";
+ interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ timer3: timer@ffefc3203c {
+ compatible = "snps,dw-apb-timer";
+ reg = <0xff 0xefc3203c 0x0 0x14>;
+ clocks = <&apb_clk>;
+ clock-names = "timer";
+ interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart4: serial@fff7f08000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0xff 0xf7f08000 0x0 0x4000>;
+ interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&uart_sclk>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart5: serial@fff7f0c000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0xff 0xf7f0c000 0x0 0x4000>;
+ interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&uart_sclk>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ timer4: timer@ffffc33000 {
+ compatible = "snps,dw-apb-timer";
+ reg = <0xff 0xffc33000 0x0 0x14>;
+ clocks = <&apb_clk>;
+ clock-names = "timer";
+ interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ timer5: timer@ffffc33014 {
+ compatible = "snps,dw-apb-timer";
+ reg = <0xff 0xffc33014 0x0 0x14>;
+ clocks = <&apb_clk>;
+ clock-names = "timer";
+ interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ timer6: timer@ffffc33028 {
+ compatible = "snps,dw-apb-timer";
+ reg = <0xff 0xffc33028 0x0 0x14>;
+ clocks = <&apb_clk>;
+ clock-names = "timer";
+ interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ timer7: timer@ffffc3303c {
+ compatible = "snps,dw-apb-timer";
+ reg = <0xff 0xffc3303c 0x0 0x14>;
+ clocks = <&apb_clk>;
+ clock-names = "timer";
+ interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ ao_gpio0: gpio@fffff41000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xff 0xfff41000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ porte: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <76 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ ao_gpio1: gpio@fffff52000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xff 0xfff52000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ portf: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+ };
+};
--
2.39.3
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 3/4] configs: th1520_lpi4a_defconfig: Add initial config
2023-07-08 11:24 [PATCH v2 0/4] riscv: Initial support for Lichee PI 4A board Yixun Lan
2023-07-08 11:24 ` [PATCH v2 1/4] riscv: t-head: licheepi4a: initial support added Yixun Lan
2023-07-08 11:24 ` [PATCH v2 2/4] riscv: dts: t-head: Add basic device tree for Sipeed Lichee PI 4A board Yixun Lan
@ 2023-07-08 11:24 ` Yixun Lan
2023-07-08 11:24 ` [PATCH v2 4/4] doc: t-head: lpi4a: document Lichee PI 4A board Yixun Lan
2023-07-13 0:24 ` [PATCH v2 0/4] riscv: Initial support for " Guo Ren
4 siblings, 0 replies; 6+ messages in thread
From: Yixun Lan @ 2023-07-08 11:24 UTC (permalink / raw)
To: u-boot; +Cc: Rick Chen, Leo, Wei Fu, Yixun Lan, Jisheng Zhang, Guo Ren
Add basic config for Sipeed Lichee PI 4A board which make it capable of
booting into serial console.
Reviewed-by: Wei Fu <wefu@redhat.com>
Signed-off-by: Yixun Lan <dlan@gentoo.org>
---
configs/th1520_lpi4a_defconfig | 82 ++++++++++++++++++++++++++++++++++
1 file changed, 82 insertions(+)
create mode 100644 configs/th1520_lpi4a_defconfig
diff --git a/configs/th1520_lpi4a_defconfig b/configs/th1520_lpi4a_defconfig
new file mode 100644
index 0000000000..710ec6abf5
--- /dev/null
+++ b/configs/th1520_lpi4a_defconfig
@@ -0,0 +1,82 @@
+CONFIG_RISCV=y
+CONFIG_SYS_MALLOC_LEN=0x800000
+CONFIG_SYS_MALLOC_F_LEN=0x3000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
+CONFIG_DEFAULT_DEVICE_TREE="th1520-lichee-pi-4a"
+CONFIG_SYS_PROMPT="LPI4A=> "
+CONFIG_SYS_LOAD_ADDR=0x80200000
+# CONFIG_SMP is not set
+CONFIG_TARGET_TH1520_LPI4A=y
+CONFIG_ARCH_RV64I=y
+CONFIG_OF_BOARD_FIXUP=y
+CONFIG_SYS_BOOT_GET_CMDLINE=y
+CONFIG_SYS_BOOT_GET_KBD=y
+CONFIG_FIT=y
+# CONFIG_FIT_FULL_CHECK is not set
+# CONFIG_FIT_PRINT is not set
+# CONFIG_BOOTSTD is not set
+# CONFIG_LEGACY_IMAGE_FORMAT is not set
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTARGS_SUBST=y
+CONFIG_BOOTCOMMAND=""
+CONFIG_DEFAULT_FDT_FILE="thead/th1520-lichee-pi-4a.dtb"
+CONFIG_LOG=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SYS_CBSIZE=256
+CONFIG_SYS_PBSIZE=276
+CONFIG_CMD_CONFIG=y
+CONFIG_CMD_LICENSE=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_CMD_BOOTMENU=y
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_MEMORY is not set
+# CONFIG_CMD_LZMADEC is not set
+# CONFIG_CMD_UNLZ4 is not set
+# CONFIG_CMD_UNZIP is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_SLEEP is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_VERSION_VARIABLE=y
+# CONFIG_NET is not set
+# CONFIG_BLOCK_CACHE is not set
+# CONFIG_GPIO is not set
+# CONFIG_I2C is not set
+# CONFIG_INPUT is not set
+# CONFIG_DM_MMC is not set
+# CONFIG_MTD is not set
+# CONFIG_POWER is not set
+CONFIG_SYS_NS16550=y
+CONFIG_RISCV_TIMER=y
+CONFIG_AES=y
+CONFIG_BLAKE2=y
+CONFIG_SHA512=y
+CONFIG_LZ4=y
+CONFIG_LZMA=y
+CONFIG_LZO=y
+CONFIG_ZLIB_UNCOMPRESS=y
+CONFIG_BZIP2=y
+CONFIG_ZSTD=y
+CONFIG_LIB_RATIONAL=y
+# CONFIG_EFI_LOADER is not set
+# CONFIG_LMB_USE_MAX_REGIONS is not set
--
2.39.3
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 4/4] doc: t-head: lpi4a: document Lichee PI 4A board
2023-07-08 11:24 [PATCH v2 0/4] riscv: Initial support for Lichee PI 4A board Yixun Lan
` (2 preceding siblings ...)
2023-07-08 11:24 ` [PATCH v2 3/4] configs: th1520_lpi4a_defconfig: Add initial config Yixun Lan
@ 2023-07-08 11:24 ` Yixun Lan
2023-07-13 0:24 ` [PATCH v2 0/4] riscv: Initial support for " Guo Ren
4 siblings, 0 replies; 6+ messages in thread
From: Yixun Lan @ 2023-07-08 11:24 UTC (permalink / raw)
To: u-boot; +Cc: Rick Chen, Leo, Wei Fu, Yixun Lan, Jisheng Zhang, Guo Ren
Reviewed-by: Wei Fu <wefu@redhat.com>
Signed-off-by: Yixun Lan <dlan@gentoo.org>
---
doc/board/index.rst | 1 +
doc/board/thead/index.rst | 9 +++
doc/board/thead/lpi4a.rst | 129 ++++++++++++++++++++++++++++++++++++++
3 files changed, 139 insertions(+)
create mode 100644 doc/board/thead/index.rst
create mode 100644 doc/board/thead/lpi4a.rst
diff --git a/doc/board/index.rst b/doc/board/index.rst
index 9ef25b1091..aadc90af89 100644
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -45,6 +45,7 @@ Board-specific doc
starfive/index
ste/index
tbs/index
+ thead/index
ti/index
toradex/index
variscite/index
diff --git a/doc/board/thead/index.rst b/doc/board/thead/index.rst
new file mode 100644
index 0000000000..41566d3a36
--- /dev/null
+++ b/doc/board/thead/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+T-HEAD
+========
+
+.. toctree::
+ :maxdepth: 1
+
+ lpi4a
diff --git a/doc/board/thead/lpi4a.rst b/doc/board/thead/lpi4a.rst
new file mode 100644
index 0000000000..e395c6ae12
--- /dev/null
+++ b/doc/board/thead/lpi4a.rst
@@ -0,0 +1,129 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Sipeed's Lichee PI 4A based on T-HEAD TH1520 SoC
+================================================
+
+The LicheePi4A is a high-performance RISC-V SBC based on TH1520(4xC910@1.85GHz),
+comes with 4/8/16 GB RAM, and up to 128GB eMMC, and rich peripherals.
+
+ - SoC T-HEAD TH1520 SoC
+ - System Memory 4GB, 8GB, or 16GB LPDDR4X
+ - Storage eMMC flash with 8/32/128 GB
+ - external microSD slot
+ - Networking 2x Gigabit Ethernet
+ - WiFi+BT
+ - Display HDMI2.0, 4-lane MIPI DSI
+ - Camera 4-lane MIPI CSI + 2x2-lane MIPI CSI
+ - Audio Onboard Speaker, 2xMEMS MIC, 3.5mm headphone jack
+ - USB 4xUSB3.0 Type-A, 1xUSB2.0 Type-C
+ - GPIO 2x10Pin breakout, UART/IIC/SPI
+ - Power DC 12V/2A, POE 5V/2.4A, USB Type-C 5V/2A
+
+TH1520 RISC-V SoC
+-----------------
+
+The TH1520 SoC consist of quad-core RISC-V Xuantie C910 (RV64GCV) processor,
+Xuantie C906 audio DSP, low power Xuantie E902 core, it also integrate
+Imagination GPU for graphics, and 4 TOPS NPU for AI acceleration.
+
+Mainline support
+----------------
+
+The support for following drivers are already enabled:
+
+1. ns16550 UART Driver.
+
+Building
+~~~~~~~~
+
+1. Add the RISC-V toolchain to your PATH.
+2. Setup ARCH & cross compilation environment variable:
+
+.. code-block:: none
+
+ export CROSS_COMPILE=<riscv64 toolchain prefix>
+
+The U-Boot is capable of running in M-Mode, so we can directly build it.
+
+.. code-block:: console
+
+ cd <U-Boot-dir>
+ make th1520_lpi4a_defconfig
+ make
+
+This will generate u-boot-dtb.bin
+
+Booting
+~~~~~~~
+
+Currently, we rely on vendor u-boot to initialize the clock, pinctrl subsystem,
+and chain load the mainline u-boot image either via tftp or emmc storage,
+then bootup from it.
+
+Sample boot log from Lichee PI 4A board via tftp
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. code-block:: none
+
+ brom_ver 8
+ [APP][E] protocol_connect failed, exit.
+
+ U-Boot SPL 2020.01-00016-g8c870a6be8 (May 20 2023 - 01:04:49 +0000)
+ FM[1] lpddr4x dualrank freq=3733 64bit dbi_off=n sdram init
+ ddr initialized, jump to uboot
+ image has no header
+
+
+ U-Boot 2020.01-00016-g8c870a6be8 (May 20 2023 - 01:04:49 +0000)
+
+ CPU: rv64imafdcvsu
+ Model: T-HEAD c910 light
+ DRAM: 8 GiB
+ C910 CPU FREQ: 750MHz
+ AHB2_CPUSYS_HCLK FREQ: 250MHz
+ AHB3_CPUSYS_PCLK FREQ: 125MHz
+ PERISYS_AHB_HCLK FREQ: 250MHz
+ PERISYS_APB_PCLK FREQ: 62MHz
+ GMAC PLL POSTDIV FREQ: 1000MHZ
+ DPU0 PLL POSTDIV FREQ: 1188MHZ
+ DPU1 PLL POSTDIV FREQ: 1188MHZ
+ MMC: sdhci@ffe7080000: 0, sd@ffe7090000: 1
+ Loading Environment from MMC... OK
+ Error reading output register
+ Warning: cannot get lcd-en GPIO
+ LCD panel cannot be found : -121
+ splash screen startup cost 16 ms
+ In: serial
+ Out: serial
+ Err: serial
+ Net:
+ Warning: ethernet@ffe7070000 using MAC address from ROM
+ eth0: ethernet@ffe7070000ethernet@ffe7070000:0 is connected to ethernet@ffe7070000. Reconnecting to ethernet@ffe7060000
+
+ Warning: ethernet@ffe7060000 (eth1) using random MAC address - 42:25:d4:16:5f:fc
+ , eth1: ethernet@ffe7060000
+ Hit any key to stop autoboot: 2
+ ethernet@ffe7060000 Waiting for PHY auto negotiation to complete.. done
+ Speed: 1000, full duplex
+ Using ethernet@ffe7070000 device
+ TFTP from server 192.168.8.50; our IP address is 192.168.8.45
+ Filename 'u-boot-dtb.bin'.
+ Load address: 0x1c00000
+ Loading: * #########################
+ 8 MiB/s
+ done
+ Bytes transferred = 376686 (5bf6e hex)
+ ## Starting application at 0x01C00000 ...
+
+ U-Boot 2023.07-rc2-00004-g1befbe31c1 (May 23 2023 - 18:40:01 +0800)
+
+ CPU: rv64imafdc
+ Model: Sipeed Lichee Pi 4A
+ DRAM: 8 GiB
+ Core: 13 devices, 6 uclasses, devicetree: separate
+ Loading Environment from <NULL>... OK
+ In: serial@ffe7014000
+ Out: serial@ffe7014000
+ Err: serial@ffe7014000
+ Model: Sipeed Lichee Pi 4A
+ LPI4A=>
--
2.39.3
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v2 0/4] riscv: Initial support for Lichee PI 4A board
2023-07-08 11:24 [PATCH v2 0/4] riscv: Initial support for Lichee PI 4A board Yixun Lan
` (3 preceding siblings ...)
2023-07-08 11:24 ` [PATCH v2 4/4] doc: t-head: lpi4a: document Lichee PI 4A board Yixun Lan
@ 2023-07-13 0:24 ` Guo Ren
4 siblings, 0 replies; 6+ messages in thread
From: Guo Ren @ 2023-07-13 0:24 UTC (permalink / raw)
To: Yixun Lan; +Cc: u-boot, Rick Chen, Leo, Wei Fu, Jisheng Zhang
For this series:
Reviewed-by: Guo Ren <guoren@kernel.org>
On Sat, Jul 8, 2023 at 7:25 AM Yixun Lan <dlan@gentoo.org> wrote:
>
> Sipeed's Lichee PI 4A board is based on T-HEAD's TH1520 SoC which consists of
> quad core XuanTie C910 CPU, plus one C906 CPU and one E902 CPU.
>
> In this series, we add a basic device tree, including UART CPU, PLIC, make it
> capable of running into a serial console.
>
> Please note that, we rely on pre shipped vendor u-boot which run in M-Mode to
> chain load this mainline u-boot either via eMMC storage or from tftp, thus the
> pinctrl and clock setting are not implemented in this series, which certainly
> can be improved later accordingly.
>
> Also the device tree is borrowed from kernel which is already accepted by kernel
> upstream [1].
>
> [1] https://lore.kernel.org/all/20230617161529.2092-1-jszhang@kernel.org
>
> Changes since PATCH v1:
> - sync device tree with mainline kernel's version
> - update docs and also fix the build error
> - fix missing <cpu_func.h> header file
>
> PATCH v1:
> https://lore.kernel.org/all/20230526124107.894-1-dlan@gentoo.org
>
> Yixun Lan (4):
> riscv: t-head: licheepi4a: initial support added
> riscv: dts: t-head: Add basic device tree for Sipeed Lichee PI 4A
> board
> configs: th1520_lpi4a_defconfig: Add initial config
> doc: t-head: lpi4a: document Lichee PI 4A board
>
> arch/riscv/Kconfig | 5 +
> arch/riscv/dts/Makefile | 1 +
> arch/riscv/dts/th1520-lichee-module-4a.dtsi | 34 ++
> arch/riscv/dts/th1520-lichee-pi-4a.dts | 32 ++
> arch/riscv/dts/th1520.dtsi | 406 ++++++++++++++++++++
> board/thead/th1520_lpi4a/Kconfig | 42 ++
> board/thead/th1520_lpi4a/MAINTAINERS | 7 +
> board/thead/th1520_lpi4a/Makefile | 5 +
> board/thead/th1520_lpi4a/board.c | 15 +
> configs/th1520_lpi4a_defconfig | 82 ++++
> doc/board/index.rst | 1 +
> doc/board/thead/index.rst | 9 +
> doc/board/thead/lpi4a.rst | 129 +++++++
> include/configs/th1520_lpi4a.h | 22 ++
> 14 files changed, 790 insertions(+)
> create mode 100644 arch/riscv/dts/th1520-lichee-module-4a.dtsi
> create mode 100644 arch/riscv/dts/th1520-lichee-pi-4a.dts
> create mode 100644 arch/riscv/dts/th1520.dtsi
> create mode 100644 board/thead/th1520_lpi4a/Kconfig
> create mode 100644 board/thead/th1520_lpi4a/MAINTAINERS
> create mode 100644 board/thead/th1520_lpi4a/Makefile
> create mode 100644 board/thead/th1520_lpi4a/board.c
> create mode 100644 configs/th1520_lpi4a_defconfig
> create mode 100644 doc/board/thead/index.rst
> create mode 100644 doc/board/thead/lpi4a.rst
> create mode 100644 include/configs/th1520_lpi4a.h
>
> --
> 2.39.3
>
--
Best Regards
Guo Ren
^ permalink raw reply [flat|nested] 6+ messages in thread