From: Andrew Cooper <andrew.cooper3@citrix.com>
To: "Marek Marczykowski-Górecki" <marmarek@invisiblethingslab.com>,
Claudia <claudia1@disroot.org>
Cc: xen-devel <xen-devel@lists.xenproject.org>,
zachm1996@gmail.com, Jan Beulich <jbeulich@suse.com>
Subject: Re: [Xen-devel] Xen fails to resume on AMD Fam15h (and Fam17h?) because of CPUID mismatch
Date: Mon, 10 Feb 2020 12:46:04 +0000 [thread overview]
Message-ID: <4e27eb03-ee21-0ab9-f225-51f5d78fe01b@citrix.com> (raw)
In-Reply-To: <20200210121443.GQ7869@mail-itl>
On 10/02/2020 12:14, Marek Marczykowski-Górecki wrote:
> On Mon, Feb 10, 2020 at 11:17:34AM +0000, Andrew Cooper wrote:
>> On 10/02/2020 08:55, Jan Beulich wrote:
>>> On 10.02.2020 00:06, Marek Marczykowski-Górecki wrote:
>>>> Hi,
>>>>
>>>> Multiple Qubes users have reported issues with resuming from S3 on AMD
>>>> systems (Ryzen 2500U, Ryzen Pro 3700U, maybe more). The error message
>>>> is:
>>>>
>>>> (XEN) CPU0: cap[ 1] is 7ed8320b (expected f6d8320b)
>>>>
>>>> If I read it right, this is:
>>>> - OSXSAVE: 0 -> 1
>>>> - HYPERVISOR: 1 -> 0
>>>>
>>>> Commenting out the panic on a failed recheck_cpu_features() in power.c
>>>> makes the system work after resume, reportedly stable. But that doesn't
>>>> sounds like a good idea generally.
>>>>
>>>> Is this difference a Xen fault (some missing MSR / other register
>>>> restore on resume)? Or BIOS vendor / AMD, that could be worked around in
>>>> Xen?
>>> The transition of the HYPERVISOR bit is definitely a Xen issue,
>>> with Andrew having sent a patch already (iirc).
>> https://lore.kernel.org/xen-devel/20200127202121.2961-1-andrew.cooper3@citrix.com/
>>
>> Code is correct. Commit message needs rework, including in light of
>> this discovery. (I may eventually split it into two patches.)
> Claudia, do you want to test with this patch?
>
>>> The OSXSAVE part is a little more surprising,
>> Not to me. The checks only care if feature bits have gone missing, not
>> if new ones have appeared.
>>
>> mmu_cr4_features includes OSXSAVE (from much later on boot than features
>> get cached), so the s3 path observing the gain of OSXSAVE will have been
>> happening ever since the checks were introduced (even on Intel.)
> Is "x86: store cr4 during suspend/resume" patch from Roger related to
> this?
No. It wouldn't have any effect on this issue, and hasn't/won't been
taken for the reasons I described out in the email chain.
~Andrew
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next prev parent reply other threads:[~2020-02-10 12:46 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-09 23:06 [Xen-devel] Xen fails to resume on AMD Fam15h (and Fam17h?) because of CPUID mismatch Marek Marczykowski-Górecki
2020-02-10 8:55 ` Jan Beulich
2020-02-10 11:17 ` Andrew Cooper
2020-02-10 12:14 ` Marek Marczykowski-Górecki
2020-02-10 12:46 ` Andrew Cooper [this message]
2020-02-11 12:59 ` Claudia
2020-02-11 21:08 ` Marek Marczykowski-Górecki
2020-02-12 4:20 ` Claudia
2020-05-02 21:12 ` Z M
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