From: Andrew Cooper <andrew.cooper3@citrix.com>
To: Jan Beulich <JBeulich@suse.com>,
xen-devel <xen-devel@lists.xenproject.org>
Cc: Brian Woods <brian.woods@amd.com>,
Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Subject: Re: [Xen-devel] [PATCH 3/9] AMD/IOMMU: use bit field for IRTE
Date: Tue, 18 Jun 2019 12:31:30 +0100 [thread overview]
Message-ID: <88756ee5-0f45-097a-3565-c15ebb9c815a@citrix.com> (raw)
In-Reply-To: <5D024E3E0200007800237E03@prv1-mh.provo.novell.com>
On 13/06/2019 14:23, Jan Beulich wrote:
> At the same time restrict its scope to just the single source file
> actually using it, and abstract accesses by introducing a union of
> pointers. (A union of the actual table entries is not used to make it
> impossible to [wrongly, once the 128-bit form gets added] perform
> pointer arithmetic / array accesses on derived types.)
>
> Also move away from updating the entries piecemeal: Construct a full new
> entry, and write it out.
>
> Signed-off-by: Jan Beulich <jbeulich@suse.com>
> ---
> It would have been nice to use write_atomic() or ACCESS_ONCE() for the
> actual writes, but both cast the value to a scalar one, which doesn't
> suit us here (and I also didn't want to make the compound type a union
> with a raw member just for this).
Actually, having looked at the following patch, I think it would be
better to union with a uint32_t raw, so that we can use...
> @@ -101,47 +118,44 @@ static unsigned int alloc_intremap_entry
> return slot;
> }
>
> -static u32 *get_intremap_entry(int seg, int bdf, int offset)
> +static union irte_ptr get_intremap_entry(unsigned int seg, unsigned int bdf,
> + unsigned int offset)
> {
> - u32 *table = get_ivrs_mappings(seg)[bdf].intremap_table;
> + union irte_ptr table = {
> + .raw = get_ivrs_mappings(seg)[bdf].intremap_table
> + };
> +
> + ASSERT(table.raw && (offset < INTREMAP_ENTRIES));
>
> - ASSERT( (table != NULL) && (offset < INTREMAP_ENTRIES) );
> + table.basic += offset;
>
> - return table + offset;
> + return table;
> }
>
> -static void free_intremap_entry(int seg, int bdf, int offset)
> +static void free_intremap_entry(unsigned int seg, unsigned int bdf, unsigned int offset)
> {
> - u32 *entry = get_intremap_entry(seg, bdf, offset);
> + union irte_ptr entry = get_intremap_entry(seg, bdf, offset);
> +
> + *entry.basic = (struct irte_basic){};
ACCESS_ONCE(*entry.basic.raw) = 0;
and...
>
> - memset(entry, 0, sizeof(u32));
> __clear_bit(offset, get_ivrs_mappings(seg)[bdf].intremap_inuse);
> }
>
> -static void update_intremap_entry(u32* entry, u8 vector, u8 int_type,
> - u8 dest_mode, u8 dest)
> -{
> - set_field_in_reg_u32(IOMMU_CONTROL_ENABLED, 0,
> - INT_REMAP_ENTRY_REMAPEN_MASK,
> - INT_REMAP_ENTRY_REMAPEN_SHIFT, entry);
> - set_field_in_reg_u32(IOMMU_CONTROL_DISABLED, *entry,
> - INT_REMAP_ENTRY_SUPIOPF_MASK,
> - INT_REMAP_ENTRY_SUPIOPF_SHIFT, entry);
> - set_field_in_reg_u32(int_type, *entry,
> - INT_REMAP_ENTRY_INTTYPE_MASK,
> - INT_REMAP_ENTRY_INTTYPE_SHIFT, entry);
> - set_field_in_reg_u32(IOMMU_CONTROL_DISABLED, *entry,
> - INT_REMAP_ENTRY_REQEOI_MASK,
> - INT_REMAP_ENTRY_REQEOI_SHIFT, entry);
> - set_field_in_reg_u32((u32)dest_mode, *entry,
> - INT_REMAP_ENTRY_DM_MASK,
> - INT_REMAP_ENTRY_DM_SHIFT, entry);
> - set_field_in_reg_u32((u32)dest, *entry,
> - INT_REMAP_ENTRY_DEST_MAST,
> - INT_REMAP_ENTRY_DEST_SHIFT, entry);
> - set_field_in_reg_u32((u32)vector, *entry,
> - INT_REMAP_ENTRY_VECTOR_MASK,
> - INT_REMAP_ENTRY_VECTOR_SHIFT, entry);
> +static void update_intremap_entry(union irte_ptr entry, unsigned int vector,
> + unsigned int int_type,
> + unsigned int dest_mode, unsigned int dest)
> +{
> + struct irte_basic basic = {
> + .remap_en = 1,
> + .sup_io_pf = 0,
> + .int_type = int_type,
> + .rq_eoi = 0,
> + .dm = dest_mode,
> + .dest = dest,
> + .vector = vector,
> + };
> +
> + *entry.basic = basic;
ACCESS_ONCE(*entry.basic.raw) = basic.raw.
The problem is in an unoptimised case, structure assignment in
implemented with memcpy(), which may be implemented as `rep stosb` which
may result in a spliced write with the enable bit set first.
Using a union with raw allows for the use of ACCESS_ONCE(), which forces
the compiler to implement them as 32bit single mov's.
~Andrew
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next prev parent reply other threads:[~2019-06-18 11:31 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-13 13:14 [Xen-devel] [PATCH 0/9] x86: AMD x2APIC support Jan Beulich
2019-06-13 13:22 ` [Xen-devel] [PATCH 1/9] AMD/IOMMU: use bit field for extended feature register Jan Beulich
2019-06-17 19:07 ` Woods, Brian
2019-06-18 9:37 ` Jan Beulich
2019-06-17 20:23 ` Andrew Cooper
2019-06-18 9:33 ` Jan Beulich
2019-06-13 13:22 ` [Xen-devel] [PATCH 2/9] AMD/IOMMU: use bit field for control register Jan Beulich
2019-06-18 9:54 ` Andrew Cooper
2019-06-18 10:45 ` Jan Beulich
2019-06-13 13:23 ` [Xen-devel] [PATCH 3/9] AMD/IOMMU: use bit field for IRTE Jan Beulich
2019-06-18 10:37 ` Andrew Cooper
2019-06-18 11:53 ` Jan Beulich
2019-06-18 12:16 ` Andrew Cooper
2019-06-18 12:55 ` Jan Beulich
2019-06-18 11:31 ` Andrew Cooper [this message]
2019-06-18 11:47 ` Jan Beulich
2019-06-13 13:23 ` [Xen-devel] [PATCH 4/9] AMD/IOMMU: introduce 128-bit IRTE non-guest-APIC IRTE format Jan Beulich
2019-06-18 11:57 ` Andrew Cooper
2019-06-18 15:31 ` Jan Beulich
2019-06-13 13:24 ` [Xen-devel] [PATCH 5/9] AMD/IOMMU: split amd_iommu_init_one() Jan Beulich
2019-06-18 12:17 ` Andrew Cooper
2019-06-13 13:25 ` [Xen-devel] [PATCH 6/9] AMD/IOMMU: allow enabling with IRQ not yet set up Jan Beulich
2019-06-18 12:22 ` Andrew Cooper
2019-06-13 13:26 ` [Xen-devel] [PATCH 7/9] AMD/IOMMU: adjust setup of internal interrupt for x2APIC mode Jan Beulich
2019-06-18 12:35 ` Andrew Cooper
2019-06-13 13:27 ` [Xen-devel] [PATCH 8/9] AMD/IOMMU: enable x2APIC mode when available Jan Beulich
2019-06-18 13:40 ` Andrew Cooper
2019-06-18 14:02 ` Jan Beulich
2019-06-13 13:28 ` [Xen-devel] [PATCH RFC 9/9] AMD/IOMMU: correct IRTE updating Jan Beulich
2019-06-18 13:28 ` Andrew Cooper
2019-06-18 14:58 ` Jan Beulich
2019-06-27 15:15 ` [Xen-devel] [PATCH v2 00/10] x86: AMD x2APIC support Jan Beulich
2019-06-27 15:19 ` [Xen-devel] [PATCH v2 01/10] AMD/IOMMU: restrict feature logging Jan Beulich
2019-07-01 15:37 ` Andrew Cooper
2019-07-01 15:59 ` Woods, Brian
2019-06-27 15:19 ` [Xen-devel] [PATCH v2 02/10] AMD/IOMMU: use bit field for extended feature register Jan Beulich
2019-07-02 12:09 ` Andrew Cooper
2019-07-02 13:48 ` Jan Beulich
2019-07-16 16:02 ` Jan Beulich
2019-06-27 15:20 ` [Xen-devel] [PATCH v2 03/10] AMD/IOMMU: use bit field for control register Jan Beulich
2019-07-02 12:20 ` Andrew Cooper
2019-06-27 15:20 ` [Xen-devel] [PATCH v2 04/10] AMD/IOMMU: use bit field for IRTE Jan Beulich
2019-07-02 12:33 ` Andrew Cooper
2019-07-02 13:56 ` Jan Beulich
2019-06-27 15:21 ` [Xen-devel] [PATCH v2 05/10] AMD/IOMMU: introduce 128-bit IRTE non-guest-APIC IRTE format Jan Beulich
2019-07-02 14:41 ` Andrew Cooper
2019-07-03 8:46 ` Jan Beulich
2019-07-16 6:39 ` Jan Beulich
2019-06-27 15:21 ` [Xen-devel] [PATCH v2 06/10] AMD/IOMMU: split amd_iommu_init_one() Jan Beulich
2019-06-27 15:22 ` [Xen-devel] [PATCH v2 07/10] AMD/IOMMU: allow enabling with IRQ not yet set up Jan Beulich
2019-06-27 15:22 ` [Xen-devel] [PATCH v2 08/10] AMD/IOMMU: adjust setup of internal interrupt for x2APIC mode Jan Beulich
2019-06-27 15:23 ` [Xen-devel] [PATCH v2 09/10] AMD/IOMMU: enable x2APIC mode when available Jan Beulich
2019-07-02 14:50 ` Andrew Cooper
2019-06-27 15:23 ` [Xen-devel] [PATCH RFC v2 10/10] AMD/IOMMU: correct IRTE updating Jan Beulich
2019-07-02 15:08 ` Andrew Cooper
2019-07-03 8:55 ` Jan Beulich
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