Re: [v2] msm: disp: dpu1: add support to access hw irqs regs depending on revision - dhar-sgV2jX0FEOL9JmXXK+q4OQ

From: dhar-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org
To: Stephen Boyd <swboyd-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org,
	robdclark-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
	nganji-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org,
	seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org,
	abhinavk-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org,
	hoegsberg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org,
	freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org,
	jsanka-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org,
	chandanu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org
Subject: Re: [v2] msm: disp: dpu1: add support to access hw irqs regs depending on revision
Date: Tue, 19 Nov 2019 12:40:58 +0000	[thread overview]
Message-ID: <0101016e83ae256e-d09a6f18-5a58-4bce-8a60-7075ef0329a4-000000@us-west-2.amazonses.com> (raw)
In-Reply-To: <5dcd8f05.1c69fb81.bdd4.2b0a-ATjtLOhZ0NVl57MIdRCFDg@public.gmane.org>

On 2019-11-14 22:59, Stephen Boyd wrote:
> Quoting Shubhashree Dhar (2019-11-13 21:56:16)
>> Current code assumes that all the irqs registers offsets can be
>> accessed in all the hw revisions; this is not the case for some
>> targets that should not access some of the irq registers.
> 
> What happens if we read the irq registers that we "should not access"?
> Does the system reset? It would be easier to make those registers 
> return
> 0 when read indicating no interrupt and ignore writes so that 
> everything
> keeps working without having to skip registers.
> 
In some of the hw revisions, the whole hw block is absent and trying to 
access those
registers causes system panic(bus noc error).

>> This change adds the support to selectively remove the irqs that
>> are not supported in some of the hw revisions.
>> 
>> Change-Id: I6052b8237b703a1a9edd53893e04f7bd72223da1
> 
> Please remove these before sending upstream.
> 
>> Signed-off-by: Shubhashree Dhar <dhar@codeaurora.org>
>> ---
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c    |  1 +
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h    |  3 +++
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 22 
>> +++++++++++++++++-----
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h |  1 +
>>  4 files changed, 22 insertions(+), 5 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h 
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> index ec76b868..def8a3f 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> @@ -646,6 +646,7 @@ struct dpu_perf_cfg {
>>   * @dma_formats        Supported formats for dma pipe
>>   * @cursor_formats     Supported formats for cursor pipe
>>   * @vig_formats        Supported formats for vig pipe
>> + * @mdss_irqs          Bitmap with the irqs supported by the target
> 
> Hmm pretty sure there needs to be a colon so that kernel-doc can match
> this but maybe I'm wrong.
> 
>>   */
>>  struct dpu_mdss_cfg {
>>         u32 hwversion;
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