Re: [RFC PATCH 5/5] x86/entry: Store CPU info on exception entry

From: Dave Hansen <dave.hansen@intel.com>
To: Ingo Molnar <mingo@kernel.org>, Ira Weiny <ira.weiny@intel.com>,
	Andy Lutomirski <luto@kernel.org>
Cc: Borislav Petkov <bp@alien8.de>, Rik van Riel <riel@surriel.com>,
	x86@kernel.org, linux-kernel@vger.kernel.org, kernel-team@fb.com
Subject: Re: [RFC PATCH 5/5] x86/entry: Store CPU info on exception entry
Date: Mon, 8 Aug 2022 09:16:43 -0700	[thread overview]
Message-ID: <01768c70-a012-0d08-cfa5-a7a87ff0a19c@intel.com> (raw)
In-Reply-To: <YvDtfKRyMGenRMU5@gmail.com>

On 8/8/22 04:03, Ingo Molnar wrote:
>> Again, I don't believe this is too much overhead but I don't want people 
>> to say it was not discussed.
> Is it necessary to do this, what are the alternatives, can this overhead be 
> avoided?

One thing Andy mentioned is that we _could_ get it down to two instructions:

	rdgsbase $reg
	push $reg

This could be hidden in:

	PUSH_PTREGS_AUXILIARY

where, today, it would only net add a single instruction.  But, if we
ever add more stuff to PUSH_PTREGS_AUXILIARY, it would move back to
needing two instructions since we'd need both the:

	subq $PTREGS_AUX_SIZE, %rsp

and something to write gsbase to the stack.

That doesn't get us the smp_processor_id() directly, but we can derive
it later on from the gsbase value.

The downside is that we're doing it in assembly.  We'd also have
something additional which is a bit uglier and that reads memory on
!X86_FEATURE_FSGSBASE, probably:

	movq    PER_CPU_VAR(cpu_number), %reg
	push %reg

Which would require some different code to decode what was there:

int read_exception_cpu_number(ext_pt_regs *e)
{
	if (cpu_feature_enabled(X86_FEATURE_FSGSBASE))
		return gsbase_to_cpu_number(e->ext_cpu_nr);
	else
		return e->ext_cpu_nr;
}

I'm thinking that the whole racy smp_processor_id() thing wasn't so bad
in the first place.