All of lore.kernel.org
 help / color / mirror / Atom feed
From: Jia Jie Ho <jiajie.ho@starfivetech.com>
To: Aurelien Jarno <aurelien@aurel32.net>,
	Palmer Dabbelt <palmer@rivosinc.com>, <olivia@selenic.com>,
	<herbert@gondor.apana.org.au>, <robh+dt@kernel.org>,
	<krzysztof.kozlowski+dt@linaro.org>, <kernel@esmil.dk>,
	Conor Dooley <conor.dooley@microchip.com>,
	<linux-crypto@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org>
Subject: Re: [PATCH v5 3/3] riscv: dts: starfive: Add TRNG node for VisionFive 2
Date: Mon, 3 Jul 2023 15:52:12 +0800	[thread overview]
Message-ID: <017dd7a1-302b-b4be-6b3d-3da0021a9b32@starfivetech.com> (raw)
In-Reply-To: <ZKCgXvcbWBGWZnsU@aurel32.net>

On 2/7/2023 5:53 am, Aurelien Jarno wrote:
> On 2023-03-14 18:45, Palmer Dabbelt wrote:
>> On Mon, 16 Jan 2023 17:54:45 PST (-0800), jiajie.ho@starfivetech.com wrote:
>> > Adding StarFive TRNG controller node to VisionFive 2 SoC.
>> > 
>> > Co-developed-by: Jenny Zhang <jenny.zhang@starfivetech.com>
>> > Signed-off-by: Jenny Zhang <jenny.zhang@starfivetech.com>
>> > Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com>
>> > ---
>> >  arch/riscv/boot/dts/starfive/jh7110.dtsi | 10 ++++++++++
>> >  1 file changed, 10 insertions(+)
>> > 
>> > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> > index 4ac159d79d66..3c29e0bc6246 100644
>> > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> > @@ -455,5 +455,15 @@ uart5: serial@12020000 {
>> >  			reg-shift = <2>;
>> >  			status = "disabled";
>> >  		};
>> > +
>> > +		rng: rng@1600c000 {
>> > +			compatible = "starfive,jh7110-trng";
>> > +			reg = <0x0 0x1600C000 0x0 0x4000>;
>> > +			clocks = <&stgcrg JH7110_STGCLK_SEC_HCLK>,
>> > +				 <&stgcrg JH7110_STGCLK_SEC_MISCAHB>;
>> > +			clock-names = "hclk", "ahb";
>> > +			resets = <&stgcrg JH7110_STGRST_SEC_TOP_HRESETN>;
>> > +			interrupts = <30>;
>> > +		};
>> >  	};
>> >  };
>> 
>> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
> 
> It appears that this patch has never been applied, although the rest of
> the series has already been merged. Unfortunately it doesn't apply
> anymore due to other changes to that file.
> 
> Could you please rebase and resend it?
> 

Hi Aurelien,

This patch is dependent on
https://patchwork.kernel.org/project/linux-riscv/patch/20230518101234.143748-2-xingyu.wu@starfivetech.com/

I'll send a new patch for this dts node after all dependencies have been merged.

Thanks,
Jia Jie

WARNING: multiple messages have this Message-ID (diff)
From: Jia Jie Ho <jiajie.ho@starfivetech.com>
To: Aurelien Jarno <aurelien@aurel32.net>,
	Palmer Dabbelt <palmer@rivosinc.com>, <olivia@selenic.com>,
	<herbert@gondor.apana.org.au>, <robh+dt@kernel.org>,
	<krzysztof.kozlowski+dt@linaro.org>, <kernel@esmil.dk>,
	Conor Dooley <conor.dooley@microchip.com>,
	<linux-crypto@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org>
Subject: Re: [PATCH v5 3/3] riscv: dts: starfive: Add TRNG node for VisionFive 2
Date: Mon, 3 Jul 2023 15:52:12 +0800	[thread overview]
Message-ID: <017dd7a1-302b-b4be-6b3d-3da0021a9b32@starfivetech.com> (raw)
In-Reply-To: <ZKCgXvcbWBGWZnsU@aurel32.net>

On 2/7/2023 5:53 am, Aurelien Jarno wrote:
> On 2023-03-14 18:45, Palmer Dabbelt wrote:
>> On Mon, 16 Jan 2023 17:54:45 PST (-0800), jiajie.ho@starfivetech.com wrote:
>> > Adding StarFive TRNG controller node to VisionFive 2 SoC.
>> > 
>> > Co-developed-by: Jenny Zhang <jenny.zhang@starfivetech.com>
>> > Signed-off-by: Jenny Zhang <jenny.zhang@starfivetech.com>
>> > Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com>
>> > ---
>> >  arch/riscv/boot/dts/starfive/jh7110.dtsi | 10 ++++++++++
>> >  1 file changed, 10 insertions(+)
>> > 
>> > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> > index 4ac159d79d66..3c29e0bc6246 100644
>> > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> > @@ -455,5 +455,15 @@ uart5: serial@12020000 {
>> >  			reg-shift = <2>;
>> >  			status = "disabled";
>> >  		};
>> > +
>> > +		rng: rng@1600c000 {
>> > +			compatible = "starfive,jh7110-trng";
>> > +			reg = <0x0 0x1600C000 0x0 0x4000>;
>> > +			clocks = <&stgcrg JH7110_STGCLK_SEC_HCLK>,
>> > +				 <&stgcrg JH7110_STGCLK_SEC_MISCAHB>;
>> > +			clock-names = "hclk", "ahb";
>> > +			resets = <&stgcrg JH7110_STGRST_SEC_TOP_HRESETN>;
>> > +			interrupts = <30>;
>> > +		};
>> >  	};
>> >  };
>> 
>> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
> 
> It appears that this patch has never been applied, although the rest of
> the series has already been merged. Unfortunately it doesn't apply
> anymore due to other changes to that file.
> 
> Could you please rebase and resend it?
> 

Hi Aurelien,

This patch is dependent on
https://patchwork.kernel.org/project/linux-riscv/patch/20230518101234.143748-2-xingyu.wu@starfivetech.com/

I'll send a new patch for this dts node after all dependencies have been merged.

Thanks,
Jia Jie

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  parent reply	other threads:[~2023-07-03  7:52 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-17  1:54 [PATCH v5 0/3] hwrng: starfive: Add driver for TRNG module Jia Jie Ho
2023-01-17  1:54 ` Jia Jie Ho
2023-01-17  1:54 ` [PATCH v5 1/3] dt-bindings: rng: Add StarFive " Jia Jie Ho
2023-01-17  1:54   ` Jia Jie Ho
2023-01-17  1:54 ` [PATCH v5 2/3] hwrng: starfive - Add TRNG driver for StarFive SoC Jia Jie Ho
2023-01-17  1:54   ` Jia Jie Ho
2023-01-27 11:03   ` [PATCH] hwrng: starfive - Enable compile testing Herbert Xu
2023-01-27 11:03     ` Herbert Xu
2023-01-27 11:13     ` Conor Dooley
2023-01-27 11:13       ` Conor Dooley
2023-01-31  7:28     ` JiaJie Ho
2023-01-31  7:28       ` JiaJie Ho
2023-01-17  1:54 ` [PATCH v5 3/3] riscv: dts: starfive: Add TRNG node for VisionFive 2 Jia Jie Ho
2023-01-17  1:54   ` Jia Jie Ho
2023-03-15  1:45   ` Palmer Dabbelt
2023-03-15  1:45     ` Palmer Dabbelt
2023-07-01 21:53     ` Aurelien Jarno
2023-07-01 21:53       ` Aurelien Jarno
2023-07-01 23:05       ` Conor Dooley
2023-07-01 23:05         ` Conor Dooley
2023-07-03  7:52       ` Jia Jie Ho [this message]
2023-07-03  7:52         ` Jia Jie Ho
2023-01-27 11:00 ` [PATCH v5 0/3] hwrng: starfive: Add driver for TRNG module Herbert Xu
2023-01-27 11:00   ` Herbert Xu

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=017dd7a1-302b-b4be-6b3d-3da0021a9b32@starfivetech.com \
    --to=jiajie.ho@starfivetech.com \
    --cc=aurelien@aurel32.net \
    --cc=conor.dooley@microchip.com \
    --cc=devicetree@vger.kernel.org \
    --cc=herbert@gondor.apana.org.au \
    --cc=kernel@esmil.dk \
    --cc=krzysztof.kozlowski+dt@linaro.org \
    --cc=linux-crypto@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-riscv@lists.infradead.org \
    --cc=olivia@selenic.com \
    --cc=palmer@rivosinc.com \
    --cc=robh+dt@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.