From: Richard Henderson <richard.henderson@linaro.org>
To: Nathan Chancellor <nathan@kernel.org>
Cc: qemu-devel@nongnu.org, Peter Maydell <peter.maydell@linaro.org>,
qemu-arm@nongnu.org, llvm@lists.linux.dev
Subject: Re: [PATCH v5 17/31] target/arm: Enforce alignment for LDM/STM
Date: Tue, 7 Sep 2021 15:44:29 +0200 [thread overview]
Message-ID: <0699da7b-354f-aecc-a62f-e25693209af4@linaro.org> (raw)
In-Reply-To: <YS19IBEGrIUnUT2p@Ryzen-9-3900X.localdomain>
On 8/31/21 2:51 AM, Nathan Chancellor wrote:
> I just bisected a boot hang with an LLVM-built multi_v7_defconfig +
> CONFIG_THUMB2_KERNEL=y kernel down to this commit. I do not see the same
> hang when the kernel is compiled with GCC 11.2.0 and binutils 2.37 nor
> do I see a hang with multi_v7_defconfig by itself. Is there something
> that LLVM is doing wrong when compiling/assembling/linking the kernel or
> is there something wrong/too aggressive with this commit? I can
> reproduce this with current QEMU HEAD (ad22d05833).
>
> My QEMU invocation is:
>
> $ qemu-system-arm \
> -append "console=ttyAMA0 earlycon" \
> -display none \
> -initrd rootfs.cpio \
> -kernel zImage \
> -M virt \
> -m 512m \
> -nodefaults \
> -no-reboot \
> -serial mon:stdio
>
> and the rootfs.cpio and zImage files can be found here:
>
> https://github.com/nathanchance/bug-files/tree/15c1fd6e44622a3c27823d2c5c3083dfc7246146/qemu-2e1f39e29bf9a6b28eaee9fc0949aab50dbad94a
Hmm. I see
IN:
0xc13038e2: e890 008c ldm.w r0, {r2, r3, r7}
R00=c13077ca R01=c11a8058 R02=c11a8058 R03=c031737f
R04=48379000 R05=00000024 R06=c031748d R07=c03174bb
R08=412fc0f1 R09=c0ce9308 R10=50c5387d R11=00000000
R12=00000009 R13=c1501f88 R14=c0301739 R15=c13038e2
PSR=200001f3 --C- T svc32
Taking exception 4 [Data Abort]
...from EL1 to EL1
...with ESR 0x25/0x9600003f
...with DFSR 0x1 DFAR 0xc13077ca
So, yes, it's a ldm from an address % 4 = 2, so it is correct that we should trap. You
should see the same trap on real hw.
r~
WARNING: multiple messages have this Message-ID (diff)
From: Richard Henderson <richard.henderson@linaro.org>
To: Nathan Chancellor <nathan@kernel.org>
Cc: Peter Maydell <peter.maydell@linaro.org>,
qemu-arm@nongnu.org, llvm@lists.linux.dev, qemu-devel@nongnu.org
Subject: Re: [PATCH v5 17/31] target/arm: Enforce alignment for LDM/STM
Date: Tue, 7 Sep 2021 15:44:29 +0200 [thread overview]
Message-ID: <0699da7b-354f-aecc-a62f-e25693209af4@linaro.org> (raw)
In-Reply-To: <YS19IBEGrIUnUT2p@Ryzen-9-3900X.localdomain>
On 8/31/21 2:51 AM, Nathan Chancellor wrote:
> I just bisected a boot hang with an LLVM-built multi_v7_defconfig +
> CONFIG_THUMB2_KERNEL=y kernel down to this commit. I do not see the same
> hang when the kernel is compiled with GCC 11.2.0 and binutils 2.37 nor
> do I see a hang with multi_v7_defconfig by itself. Is there something
> that LLVM is doing wrong when compiling/assembling/linking the kernel or
> is there something wrong/too aggressive with this commit? I can
> reproduce this with current QEMU HEAD (ad22d05833).
>
> My QEMU invocation is:
>
> $ qemu-system-arm \
> -append "console=ttyAMA0 earlycon" \
> -display none \
> -initrd rootfs.cpio \
> -kernel zImage \
> -M virt \
> -m 512m \
> -nodefaults \
> -no-reboot \
> -serial mon:stdio
>
> and the rootfs.cpio and zImage files can be found here:
>
> https://github.com/nathanchance/bug-files/tree/15c1fd6e44622a3c27823d2c5c3083dfc7246146/qemu-2e1f39e29bf9a6b28eaee9fc0949aab50dbad94a
Hmm. I see
IN:
0xc13038e2: e890 008c ldm.w r0, {r2, r3, r7}
R00=c13077ca R01=c11a8058 R02=c11a8058 R03=c031737f
R04=48379000 R05=00000024 R06=c031748d R07=c03174bb
R08=412fc0f1 R09=c0ce9308 R10=50c5387d R11=00000000
R12=00000009 R13=c1501f88 R14=c0301739 R15=c13038e2
PSR=200001f3 --C- T svc32
Taking exception 4 [Data Abort]
...from EL1 to EL1
...with ESR 0x25/0x9600003f
...with DFSR 0x1 DFAR 0xc13077ca
So, yes, it's a ldm from an address % 4 = 2, so it is correct that we should trap. You
should see the same trap on real hw.
r~
next prev parent reply other threads:[~2021-09-07 13:44 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-19 20:22 [PATCH v5 00/31] target/arm: enforce alignment Richard Henderson
2021-04-19 20:22 ` [PATCH v5 01/31] target/arm: Fix decode of align in VLDST_single Richard Henderson
2021-04-19 20:22 ` [PATCH v5 02/31] target/arm: Rename TBFLAG_A32, SCTLR_B Richard Henderson
2021-04-19 20:22 ` [PATCH v5 03/31] target/arm: Rename TBFLAG_ANY, PSTATE_SS Richard Henderson
2021-04-19 20:22 ` [PATCH v5 04/31] target/arm: Add wrapper macros for accessing tbflags Richard Henderson
2021-04-19 20:22 ` [PATCH v5 05/31] target/arm: Introduce CPUARMTBFlags Richard Henderson
2021-04-19 20:22 ` [PATCH v5 06/31] target/arm: Move mode specific TB flags to tb->cs_base Richard Henderson
2021-04-19 20:22 ` [PATCH v5 07/31] target/arm: Use cpu_abort in assert_hflags_rebuild_correctly Richard Henderson
2021-04-20 9:07 ` Peter Maydell
2021-04-19 20:22 ` [PATCH v5 08/31] target/arm: Move TBFLAG_AM32 bits to the top Richard Henderson
2021-04-19 20:22 ` [PATCH v5 09/31] target/arm: Move TBFLAG_ANY bits to the bottom Richard Henderson
2021-04-19 20:22 ` [PATCH v5 10/31] target/arm: Add ALIGN_MEM to TBFLAG_ANY Richard Henderson
2021-04-19 20:22 ` [PATCH v5 11/31] target/arm: Adjust gen_aa32_{ld, st}_i32 for align+endianness Richard Henderson
2021-04-19 20:22 ` [PATCH v5 12/31] target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64 Richard Henderson
2021-04-19 20:22 ` [PATCH v5 13/31] target/arm: Fix SCTLR_B test for TCGv_i64 load/store Richard Henderson
2021-04-19 20:22 ` [PATCH v5 14/31] target/arm: Adjust gen_aa32_{ld, st}_i64 for align+endianness Richard Henderson
2021-04-19 20:22 ` [PATCH v5 15/31] target/arm: Enforce word alignment for LDRD/STRD Richard Henderson
2021-04-19 20:22 ` [PATCH v5 16/31] target/arm: Enforce alignment for LDA/LDAH/STL/STLH Richard Henderson
2021-04-19 20:22 ` [PATCH v5 17/31] target/arm: Enforce alignment for LDM/STM Richard Henderson
2021-08-31 0:51 ` Nathan Chancellor
2021-08-31 0:51 ` Nathan Chancellor
2021-09-07 13:44 ` Richard Henderson [this message]
2021-09-07 13:44 ` Richard Henderson
2021-09-15 1:13 ` Nick Desaulniers
2021-09-15 1:13 ` Nick Desaulniers
2021-04-19 20:22 ` [PATCH v5 18/31] target/arm: Enforce alignment for RFE Richard Henderson
2021-04-19 20:22 ` [PATCH v5 19/31] target/arm: Enforce alignment for SRS Richard Henderson
2021-04-19 20:22 ` [PATCH v5 20/31] target/arm: Enforce alignment for VLDM/VSTM Richard Henderson
2021-04-19 20:22 ` [PATCH v5 21/31] target/arm: Enforce alignment for VLDR/VSTR Richard Henderson
2021-04-19 20:22 ` [PATCH v5 22/31] target/arm: Enforce alignment for VLDn (all lanes) Richard Henderson
2021-04-19 20:22 ` [PATCH v5 23/31] target/arm: Enforce alignment for VLDn/VSTn (multiple) Richard Henderson
2021-04-19 20:22 ` [PATCH v5 24/31] target/arm: Enforce alignment for VLDn/VSTn (single) Richard Henderson
2021-04-19 20:22 ` [PATCH v5 25/31] target/arm: Use finalize_memop for aa64 gpr load/store Richard Henderson
2021-04-19 20:22 ` [PATCH v5 26/31] target/arm: Use finalize_memop for aa64 fpr load/store Richard Henderson
2021-04-19 20:22 ` [PATCH v5 27/31] target/arm: Enforce alignment for aa64 load-acq/store-rel Richard Henderson
2021-04-19 20:22 ` [PATCH v5 28/31] target/arm: Use MemOp for size + endian in aa64 vector ld/st Richard Henderson
2021-04-19 20:22 ` [PATCH v5 29/31] target/arm: Enforce alignment for aa64 vector LDn/STn (multiple) Richard Henderson
2021-04-19 20:22 ` [PATCH v5 30/31] target/arm: Enforce alignment for aa64 vector LDn/STn (single) Richard Henderson
2021-04-19 20:22 ` [PATCH v5 31/31] target/arm: Enforce alignment for sve LD1R Richard Henderson
2021-04-20 10:27 ` [PATCH v5 00/31] target/arm: enforce alignment Peter Maydell
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=0699da7b-354f-aecc-a62f-e25693209af4@linaro.org \
--to=richard.henderson@linaro.org \
--cc=llvm@lists.linux.dev \
--cc=nathan@kernel.org \
--cc=peter.maydell@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.