From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> To: Johnson Wang <johnson.wang@mediatek.com>, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, sboyd@kernel.org Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Project_Global_Chrome_Upstream_Group@mediatek.com, Edward-JW Yang <edward-jw.yang@mediatek.com> Subject: Re: [PATCH v2 2/4] dt-bindings: arm: mediatek: Add new bindings of MediaTek frequency hopping Date: Wed, 14 Sep 2022 15:46:41 +0200 [thread overview] Message-ID: <06eb15ea-56b3-4f18-be18-3fc710cef779@collabora.com> (raw) In-Reply-To: <20220914124552.16964-3-johnson.wang@mediatek.com> Il 14/09/22 14:45, Johnson Wang ha scritto: > Add the new binding documentation for MediaTek frequency hopping > and spread spectrum clocking control. > > Co-developed-by: Edward-JW Yang <edward-jw.yang@mediatek.com> > Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.com> > Signed-off-by: Johnson Wang <johnson.wang@mediatek.com> > --- > .../bindings/arm/mediatek/mediatek,fhctl.yaml | 47 +++++++++++++++++++ > 1 file changed, 47 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,fhctl.yaml > > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,fhctl.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,fhctl.yaml > new file mode 100644 > index 000000000000..7b0fd0889bb6 > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,fhctl.yaml > @@ -0,0 +1,47 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,fhctl.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek frequency hopping and spread spectrum clocking control > + > +maintainers: > + - Edward-JW Yang <edward-jw.yang@mediatek.com> > + > +description: | > + Frequency hopping control (FHCTL) is a piece of hardware that control > + some PLLs to adopt "hopping" mechanism to adjust their frequency. > + Spread spectrum clocking (SSC) is another function provided by this hardware. > + > +properties: > + compatible: > + const: mediatek,mt8186-fhctl > + > + reg: > + maxItems: 1 There are still a few issues in this binding that I can immediately see... > + > + clocks: MT8195 has 23 PLLs, MT8186 has 14, but perhaps in the future we may see something more than that on some newer SoC, so... clocks: maxItems: 30 > + description: Phandles of the PLL with FHCTL hardware capability. > + > + mediatek,hopping-ssc-percents: > + description: The percentage of spread spectrum clocking for one PLL. > + $ref: /schemas/types.yaml#/definitions/uint32 This is an array, so... $ref: /schemas/types.yaml#/definitions/uint32-array ...also, maxItems? and you should also specify: default: 0 <- because, by default, SSC is disabled minimum: 0 <- because this is the minimum accepted value Regards, Angelo > + maximum: 8 > + > +required: > + - compatible > + - reg > + - clocks > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/mt8186-clk.h> > + fhctl: fhctl@1000ce00 { > + compatible = "mediatek,mt8186-fhctl"; > + reg = <0x1000c000 0xe00>; > + clocks = <&apmixedsys CLK_APMIXED_MSDCPLL>; > + mediatek,hopping-ssc-percents = <3>; > + };
WARNING: multiple messages have this Message-ID (diff)
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> To: Johnson Wang <johnson.wang@mediatek.com>, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, sboyd@kernel.org Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Project_Global_Chrome_Upstream_Group@mediatek.com, Edward-JW Yang <edward-jw.yang@mediatek.com> Subject: Re: [PATCH v2 2/4] dt-bindings: arm: mediatek: Add new bindings of MediaTek frequency hopping Date: Wed, 14 Sep 2022 15:46:41 +0200 [thread overview] Message-ID: <06eb15ea-56b3-4f18-be18-3fc710cef779@collabora.com> (raw) In-Reply-To: <20220914124552.16964-3-johnson.wang@mediatek.com> Il 14/09/22 14:45, Johnson Wang ha scritto: > Add the new binding documentation for MediaTek frequency hopping > and spread spectrum clocking control. > > Co-developed-by: Edward-JW Yang <edward-jw.yang@mediatek.com> > Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.com> > Signed-off-by: Johnson Wang <johnson.wang@mediatek.com> > --- > .../bindings/arm/mediatek/mediatek,fhctl.yaml | 47 +++++++++++++++++++ > 1 file changed, 47 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,fhctl.yaml > > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,fhctl.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,fhctl.yaml > new file mode 100644 > index 000000000000..7b0fd0889bb6 > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,fhctl.yaml > @@ -0,0 +1,47 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,fhctl.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek frequency hopping and spread spectrum clocking control > + > +maintainers: > + - Edward-JW Yang <edward-jw.yang@mediatek.com> > + > +description: | > + Frequency hopping control (FHCTL) is a piece of hardware that control > + some PLLs to adopt "hopping" mechanism to adjust their frequency. > + Spread spectrum clocking (SSC) is another function provided by this hardware. > + > +properties: > + compatible: > + const: mediatek,mt8186-fhctl > + > + reg: > + maxItems: 1 There are still a few issues in this binding that I can immediately see... > + > + clocks: MT8195 has 23 PLLs, MT8186 has 14, but perhaps in the future we may see something more than that on some newer SoC, so... clocks: maxItems: 30 > + description: Phandles of the PLL with FHCTL hardware capability. > + > + mediatek,hopping-ssc-percents: > + description: The percentage of spread spectrum clocking for one PLL. > + $ref: /schemas/types.yaml#/definitions/uint32 This is an array, so... $ref: /schemas/types.yaml#/definitions/uint32-array ...also, maxItems? and you should also specify: default: 0 <- because, by default, SSC is disabled minimum: 0 <- because this is the minimum accepted value Regards, Angelo > + maximum: 8 > + > +required: > + - compatible > + - reg > + - clocks > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/mt8186-clk.h> > + fhctl: fhctl@1000ce00 { > + compatible = "mediatek,mt8186-fhctl"; > + reg = <0x1000c000 0xe00>; > + clocks = <&apmixedsys CLK_APMIXED_MSDCPLL>; > + mediatek,hopping-ssc-percents = <3>; > + }; _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-09-14 13:46 UTC|newest] Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-09-14 12:45 [PATCH v2 0/4] Introduce MediaTek frequency hopping driver Johnson Wang 2022-09-14 12:45 ` Johnson Wang 2022-09-14 12:45 ` [PATCH v2 1/4] clk: mediatek: Export PLL operations symbols Johnson Wang 2022-09-14 12:45 ` Johnson Wang 2022-09-14 12:45 ` [PATCH v2 2/4] dt-bindings: arm: mediatek: Add new bindings of MediaTek frequency hopping Johnson Wang 2022-09-14 12:45 ` Johnson Wang 2022-09-14 13:46 ` AngeloGioacchino Del Regno [this message] 2022-09-14 13:46 ` AngeloGioacchino Del Regno 2022-09-15 4:00 ` Johnson Wang 2022-09-15 4:00 ` Johnson Wang 2022-09-15 6:56 ` AngeloGioacchino Del Regno 2022-09-15 6:56 ` AngeloGioacchino Del Regno 2022-09-18 9:38 ` Krzysztof Kozlowski 2022-09-18 9:38 ` Krzysztof Kozlowski 2022-09-28 6:18 ` Johnson Wang (王聖鑫) 2022-09-28 6:18 ` Johnson Wang (王聖鑫) 2022-09-14 12:45 ` [PATCH v2 3/4] clk: mediatek: Add new clock driver to handle FHCTL hardware Johnson Wang 2022-09-14 12:45 ` Johnson Wang 2022-09-27 10:56 ` Edward-JW Yang 2022-09-27 10:56 ` Edward-JW Yang 2022-09-28 6:18 ` Johnson Wang (王聖鑫) 2022-09-28 6:18 ` Johnson Wang (王聖鑫) 2022-09-14 12:45 ` [PATCH v2 4/4] clk: mediatek: Change PLL register API for MT8186 Johnson Wang 2022-09-14 12:45 ` Johnson Wang
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