From: abhinavk@codeaurora.org
To: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>,
David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
Stephen Boyd <swboyd@chromium.org>,
sbillaka@codeaurora.org, Tanmay Shah <tanmay@codeaurora.org>,
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
dri-devel@lists.freedesktop.org,
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
freedreno@lists.freedesktop.org,
Chandan Uddaraju <chandanu@codeaurora.org>
Subject: Re: [Freedreno] [PATCH 2/4] drm/msm/dp: Store each subblock in the io region
Date: Fri, 28 May 2021 16:14:59 -0700 [thread overview]
Message-ID: <0a2e38497feb4b6904f5e5bc3ed43c62@codeaurora.org> (raw)
In-Reply-To: <20210511042043.592802-3-bjorn.andersson@linaro.org>
On 2021-05-10 21:20, Bjorn Andersson wrote:
> Not all platforms has DP_P0 at offset 0x1000 from the beginning of the
> DP block. So move the offsets into dss_io_data, to make it possible in
> the next patch to specify alternative offsets and sizes of these
> segments.
>
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> ---
> drivers/gpu/drm/msm/dp/dp_catalog.c | 57 ++++++++---------------------
> drivers/gpu/drm/msm/dp/dp_parser.c | 10 +++++
> drivers/gpu/drm/msm/dp/dp_parser.h | 8 ++++
> 3 files changed, 33 insertions(+), 42 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c
> b/drivers/gpu/drm/msm/dp/dp_catalog.c
> index 2eb37ee48e42..a0449a2867e4 100644
> --- a/drivers/gpu/drm/msm/dp/dp_catalog.c
> +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c
> @@ -24,15 +24,6 @@
> #define DP_INTERRUPT_STATUS_ACK_SHIFT 1
> #define DP_INTERRUPT_STATUS_MASK_SHIFT 2
>
> -#define MSM_DP_CONTROLLER_AHB_OFFSET 0x0000
> -#define MSM_DP_CONTROLLER_AHB_SIZE 0x0200
> -#define MSM_DP_CONTROLLER_AUX_OFFSET 0x0200
> -#define MSM_DP_CONTROLLER_AUX_SIZE 0x0200
> -#define MSM_DP_CONTROLLER_LINK_OFFSET 0x0400
> -#define MSM_DP_CONTROLLER_LINK_SIZE 0x0C00
> -#define MSM_DP_CONTROLLER_P0_OFFSET 0x1000
> -#define MSM_DP_CONTROLLER_P0_SIZE 0x0400
> -
> #define DP_INTERRUPT_STATUS1 \
> (DP_INTR_AUX_I2C_DONE| \
> DP_INTR_WRONG_ADDR | DP_INTR_TIMEOUT | \
> @@ -64,75 +55,67 @@ struct dp_catalog_private {
>
> static inline u32 dp_read_aux(struct dp_catalog_private *catalog, u32
> offset)
> {
> - offset += MSM_DP_CONTROLLER_AUX_OFFSET;
> - return readl_relaxed(catalog->io->dp_controller.base + offset);
> + return readl_relaxed(catalog->io->dp_controller.aux + offset);
> }
>
> static inline void dp_write_aux(struct dp_catalog_private *catalog,
> u32 offset, u32 data)
> {
> - offset += MSM_DP_CONTROLLER_AUX_OFFSET;
> /*
> * To make sure aux reg writes happens before any other operation,
> * this function uses writel() instread of writel_relaxed()
> */
> - writel(data, catalog->io->dp_controller.base + offset);
> + writel(data, catalog->io->dp_controller.aux + offset);
> }
>
> static inline u32 dp_read_ahb(struct dp_catalog_private *catalog, u32
> offset)
> {
> - offset += MSM_DP_CONTROLLER_AHB_OFFSET;
> - return readl_relaxed(catalog->io->dp_controller.base + offset);
> + return readl_relaxed(catalog->io->dp_controller.ahb + offset);
> }
>
> static inline void dp_write_ahb(struct dp_catalog_private *catalog,
> u32 offset, u32 data)
> {
> - offset += MSM_DP_CONTROLLER_AHB_OFFSET;
> /*
> * To make sure phy reg writes happens before any other operation,
> * this function uses writel() instread of writel_relaxed()
> */
> - writel(data, catalog->io->dp_controller.base + offset);
> + writel(data, catalog->io->dp_controller.ahb + offset);
> }
>
> static inline void dp_write_p0(struct dp_catalog_private *catalog,
> u32 offset, u32 data)
> {
> - offset += MSM_DP_CONTROLLER_P0_OFFSET;
> /*
> * To make sure interface reg writes happens before any other
> operation,
> * this function uses writel() instread of writel_relaxed()
> */
> - writel(data, catalog->io->dp_controller.base + offset);
> + writel(data, catalog->io->dp_controller.p0 + offset);
> }
>
> static inline u32 dp_read_p0(struct dp_catalog_private *catalog,
> u32 offset)
> {
> - offset += MSM_DP_CONTROLLER_P0_OFFSET;
> /*
> * To make sure interface reg writes happens before any other
> operation,
> * this function uses writel() instread of writel_relaxed()
> */
> - return readl_relaxed(catalog->io->dp_controller.base + offset);
> + return readl_relaxed(catalog->io->dp_controller.p0 + offset);
> }
>
> static inline u32 dp_read_link(struct dp_catalog_private *catalog, u32
> offset)
> {
> - offset += MSM_DP_CONTROLLER_LINK_OFFSET;
> - return readl_relaxed(catalog->io->dp_controller.base + offset);
> + return readl_relaxed(catalog->io->dp_controller.link + offset);
> }
>
> static inline void dp_write_link(struct dp_catalog_private *catalog,
> u32 offset, u32 data)
> {
> - offset += MSM_DP_CONTROLLER_LINK_OFFSET;
> /*
> * To make sure link reg writes happens before any other operation,
> * this function uses writel() instread of writel_relaxed()
> */
> - writel(data, catalog->io->dp_controller.base + offset);
> + writel(data, catalog->io->dp_controller.link + offset);
> }
>
> /* aux related catalog functions */
> @@ -267,29 +250,21 @@ static void dump_regs(void __iomem *base, int
> len)
>
> void dp_catalog_dump_regs(struct dp_catalog *dp_catalog)
> {
> - u32 offset, len;
> struct dp_catalog_private *catalog = container_of(dp_catalog,
> struct dp_catalog_private, dp_catalog);
> + struct dss_io_data *io = &catalog->io->dp_controller;
>
> pr_info("AHB regs\n");
> - offset = MSM_DP_CONTROLLER_AHB_OFFSET;
> - len = MSM_DP_CONTROLLER_AHB_SIZE;
> - dump_regs(catalog->io->dp_controller.base + offset, len);
> + dump_regs(io->ahb, io->ahb_len);
>
> pr_info("AUXCLK regs\n");
> - offset = MSM_DP_CONTROLLER_AUX_OFFSET;
> - len = MSM_DP_CONTROLLER_AUX_SIZE;
> - dump_regs(catalog->io->dp_controller.base + offset, len);
> + dump_regs(io->aux, io->aux_len);
>
> pr_info("LCLK regs\n");
> - offset = MSM_DP_CONTROLLER_LINK_OFFSET;
> - len = MSM_DP_CONTROLLER_LINK_SIZE;
> - dump_regs(catalog->io->dp_controller.base + offset, len);
> + dump_regs(io->link, io->link_len);
>
> pr_info("P0CLK regs\n");
> - offset = MSM_DP_CONTROLLER_P0_OFFSET;
> - len = MSM_DP_CONTROLLER_P0_SIZE;
> - dump_regs(catalog->io->dp_controller.base + offset, len);
> + dump_regs(io->p0, io->p0_len);
> }
>
> int dp_catalog_aux_get_irq(struct dp_catalog *dp_catalog)
> @@ -454,8 +429,7 @@ int dp_catalog_ctrl_set_pattern(struct dp_catalog
> *dp_catalog,
> bit = BIT(pattern - 1) << DP_MAINLINK_READY_LINK_TRAINING_SHIFT;
>
> /* Poll for mainlink ready status */
> - ret = readx_poll_timeout(readl, catalog->io->dp_controller.base +
> - MSM_DP_CONTROLLER_LINK_OFFSET +
> + ret = readx_poll_timeout(readl, catalog->io->dp_controller.link +
> REG_DP_MAINLINK_READY,
> data, data & bit,
> POLLING_SLEEP_US, POLLING_TIMEOUT_US);
> @@ -502,8 +476,7 @@ bool dp_catalog_ctrl_mainlink_ready(struct
> dp_catalog *dp_catalog)
> struct dp_catalog_private, dp_catalog);
>
> /* Poll for mainlink ready status */
> - ret = readl_poll_timeout(catalog->io->dp_controller.base +
> - MSM_DP_CONTROLLER_LINK_OFFSET +
> + ret = readl_poll_timeout(catalog->io->dp_controller.link +
> REG_DP_MAINLINK_READY,
> data, data & DP_MAINLINK_READY_FOR_VIDEO,
> POLLING_SLEEP_US, POLLING_TIMEOUT_US);
> diff --git a/drivers/gpu/drm/msm/dp/dp_parser.c
> b/drivers/gpu/drm/msm/dp/dp_parser.c
> index 0519dd3ac3c3..51ec85b4803b 100644
> --- a/drivers/gpu/drm/msm/dp/dp_parser.c
> +++ b/drivers/gpu/drm/msm/dp/dp_parser.c
> @@ -250,6 +250,7 @@ static int dp_parser_clock(struct dp_parser
> *parser)
>
> static int dp_parser_parse(struct dp_parser *parser)
> {
> + struct dss_io_data *io = &parser->io.dp_controller;
> int rc = 0;
>
> if (!parser) {
> @@ -275,6 +276,15 @@ static int dp_parser_parse(struct dp_parser
> *parser)
> */
> parser->regulator_cfg = &sdm845_dp_reg_cfg;
>
> + io->ahb = io->base + 0x0;
> + io->ahb_len = 0x200;
> + io->aux = io->base + 0x200;
> + io->aux_len = 0x200;
> + io->link = io->base + 0x400;
> + io->link_len = 0x600;
> + io->p0 = io->base + 0x1000;
> + io->p0_len = 0x400;
> +
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/msm/dp/dp_parser.h
> b/drivers/gpu/drm/msm/dp/dp_parser.h
> index 34b49628bbaf..ff4774109c63 100644
> --- a/drivers/gpu/drm/msm/dp/dp_parser.h
> +++ b/drivers/gpu/drm/msm/dp/dp_parser.h
> @@ -28,6 +28,14 @@ enum dp_pm_type {
> struct dss_io_data {
> u32 len;
> void __iomem *base;
> + void __iomem *ahb;
> + size_t ahb_len;
> + void __iomem *aux;
> + size_t aux_len;
> + void __iomem *link;
> + size_t link_len;
> + void __iomem *p0;
> + size_t p0_len;
> };
>
> static inline const char *dp_parser_pm_name(enum dp_pm_type module)
WARNING: multiple messages have this Message-ID (diff)
From: abhinavk@codeaurora.org
To: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: freedreno@lists.freedesktop.org, David Airlie <airlied@linux.ie>,
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
Tanmay Shah <tanmay@codeaurora.org>,
Stephen Boyd <swboyd@chromium.org>,
dri-devel@lists.freedesktop.org,
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
sbillaka@codeaurora.org, Sean Paul <sean@poorly.run>,
Chandan Uddaraju <chandanu@codeaurora.org>
Subject: Re: [Freedreno] [PATCH 2/4] drm/msm/dp: Store each subblock in the io region
Date: Fri, 28 May 2021 16:14:59 -0700 [thread overview]
Message-ID: <0a2e38497feb4b6904f5e5bc3ed43c62@codeaurora.org> (raw)
In-Reply-To: <20210511042043.592802-3-bjorn.andersson@linaro.org>
On 2021-05-10 21:20, Bjorn Andersson wrote:
> Not all platforms has DP_P0 at offset 0x1000 from the beginning of the
> DP block. So move the offsets into dss_io_data, to make it possible in
> the next patch to specify alternative offsets and sizes of these
> segments.
>
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> ---
> drivers/gpu/drm/msm/dp/dp_catalog.c | 57 ++++++++---------------------
> drivers/gpu/drm/msm/dp/dp_parser.c | 10 +++++
> drivers/gpu/drm/msm/dp/dp_parser.h | 8 ++++
> 3 files changed, 33 insertions(+), 42 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c
> b/drivers/gpu/drm/msm/dp/dp_catalog.c
> index 2eb37ee48e42..a0449a2867e4 100644
> --- a/drivers/gpu/drm/msm/dp/dp_catalog.c
> +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c
> @@ -24,15 +24,6 @@
> #define DP_INTERRUPT_STATUS_ACK_SHIFT 1
> #define DP_INTERRUPT_STATUS_MASK_SHIFT 2
>
> -#define MSM_DP_CONTROLLER_AHB_OFFSET 0x0000
> -#define MSM_DP_CONTROLLER_AHB_SIZE 0x0200
> -#define MSM_DP_CONTROLLER_AUX_OFFSET 0x0200
> -#define MSM_DP_CONTROLLER_AUX_SIZE 0x0200
> -#define MSM_DP_CONTROLLER_LINK_OFFSET 0x0400
> -#define MSM_DP_CONTROLLER_LINK_SIZE 0x0C00
> -#define MSM_DP_CONTROLLER_P0_OFFSET 0x1000
> -#define MSM_DP_CONTROLLER_P0_SIZE 0x0400
> -
> #define DP_INTERRUPT_STATUS1 \
> (DP_INTR_AUX_I2C_DONE| \
> DP_INTR_WRONG_ADDR | DP_INTR_TIMEOUT | \
> @@ -64,75 +55,67 @@ struct dp_catalog_private {
>
> static inline u32 dp_read_aux(struct dp_catalog_private *catalog, u32
> offset)
> {
> - offset += MSM_DP_CONTROLLER_AUX_OFFSET;
> - return readl_relaxed(catalog->io->dp_controller.base + offset);
> + return readl_relaxed(catalog->io->dp_controller.aux + offset);
> }
>
> static inline void dp_write_aux(struct dp_catalog_private *catalog,
> u32 offset, u32 data)
> {
> - offset += MSM_DP_CONTROLLER_AUX_OFFSET;
> /*
> * To make sure aux reg writes happens before any other operation,
> * this function uses writel() instread of writel_relaxed()
> */
> - writel(data, catalog->io->dp_controller.base + offset);
> + writel(data, catalog->io->dp_controller.aux + offset);
> }
>
> static inline u32 dp_read_ahb(struct dp_catalog_private *catalog, u32
> offset)
> {
> - offset += MSM_DP_CONTROLLER_AHB_OFFSET;
> - return readl_relaxed(catalog->io->dp_controller.base + offset);
> + return readl_relaxed(catalog->io->dp_controller.ahb + offset);
> }
>
> static inline void dp_write_ahb(struct dp_catalog_private *catalog,
> u32 offset, u32 data)
> {
> - offset += MSM_DP_CONTROLLER_AHB_OFFSET;
> /*
> * To make sure phy reg writes happens before any other operation,
> * this function uses writel() instread of writel_relaxed()
> */
> - writel(data, catalog->io->dp_controller.base + offset);
> + writel(data, catalog->io->dp_controller.ahb + offset);
> }
>
> static inline void dp_write_p0(struct dp_catalog_private *catalog,
> u32 offset, u32 data)
> {
> - offset += MSM_DP_CONTROLLER_P0_OFFSET;
> /*
> * To make sure interface reg writes happens before any other
> operation,
> * this function uses writel() instread of writel_relaxed()
> */
> - writel(data, catalog->io->dp_controller.base + offset);
> + writel(data, catalog->io->dp_controller.p0 + offset);
> }
>
> static inline u32 dp_read_p0(struct dp_catalog_private *catalog,
> u32 offset)
> {
> - offset += MSM_DP_CONTROLLER_P0_OFFSET;
> /*
> * To make sure interface reg writes happens before any other
> operation,
> * this function uses writel() instread of writel_relaxed()
> */
> - return readl_relaxed(catalog->io->dp_controller.base + offset);
> + return readl_relaxed(catalog->io->dp_controller.p0 + offset);
> }
>
> static inline u32 dp_read_link(struct dp_catalog_private *catalog, u32
> offset)
> {
> - offset += MSM_DP_CONTROLLER_LINK_OFFSET;
> - return readl_relaxed(catalog->io->dp_controller.base + offset);
> + return readl_relaxed(catalog->io->dp_controller.link + offset);
> }
>
> static inline void dp_write_link(struct dp_catalog_private *catalog,
> u32 offset, u32 data)
> {
> - offset += MSM_DP_CONTROLLER_LINK_OFFSET;
> /*
> * To make sure link reg writes happens before any other operation,
> * this function uses writel() instread of writel_relaxed()
> */
> - writel(data, catalog->io->dp_controller.base + offset);
> + writel(data, catalog->io->dp_controller.link + offset);
> }
>
> /* aux related catalog functions */
> @@ -267,29 +250,21 @@ static void dump_regs(void __iomem *base, int
> len)
>
> void dp_catalog_dump_regs(struct dp_catalog *dp_catalog)
> {
> - u32 offset, len;
> struct dp_catalog_private *catalog = container_of(dp_catalog,
> struct dp_catalog_private, dp_catalog);
> + struct dss_io_data *io = &catalog->io->dp_controller;
>
> pr_info("AHB regs\n");
> - offset = MSM_DP_CONTROLLER_AHB_OFFSET;
> - len = MSM_DP_CONTROLLER_AHB_SIZE;
> - dump_regs(catalog->io->dp_controller.base + offset, len);
> + dump_regs(io->ahb, io->ahb_len);
>
> pr_info("AUXCLK regs\n");
> - offset = MSM_DP_CONTROLLER_AUX_OFFSET;
> - len = MSM_DP_CONTROLLER_AUX_SIZE;
> - dump_regs(catalog->io->dp_controller.base + offset, len);
> + dump_regs(io->aux, io->aux_len);
>
> pr_info("LCLK regs\n");
> - offset = MSM_DP_CONTROLLER_LINK_OFFSET;
> - len = MSM_DP_CONTROLLER_LINK_SIZE;
> - dump_regs(catalog->io->dp_controller.base + offset, len);
> + dump_regs(io->link, io->link_len);
>
> pr_info("P0CLK regs\n");
> - offset = MSM_DP_CONTROLLER_P0_OFFSET;
> - len = MSM_DP_CONTROLLER_P0_SIZE;
> - dump_regs(catalog->io->dp_controller.base + offset, len);
> + dump_regs(io->p0, io->p0_len);
> }
>
> int dp_catalog_aux_get_irq(struct dp_catalog *dp_catalog)
> @@ -454,8 +429,7 @@ int dp_catalog_ctrl_set_pattern(struct dp_catalog
> *dp_catalog,
> bit = BIT(pattern - 1) << DP_MAINLINK_READY_LINK_TRAINING_SHIFT;
>
> /* Poll for mainlink ready status */
> - ret = readx_poll_timeout(readl, catalog->io->dp_controller.base +
> - MSM_DP_CONTROLLER_LINK_OFFSET +
> + ret = readx_poll_timeout(readl, catalog->io->dp_controller.link +
> REG_DP_MAINLINK_READY,
> data, data & bit,
> POLLING_SLEEP_US, POLLING_TIMEOUT_US);
> @@ -502,8 +476,7 @@ bool dp_catalog_ctrl_mainlink_ready(struct
> dp_catalog *dp_catalog)
> struct dp_catalog_private, dp_catalog);
>
> /* Poll for mainlink ready status */
> - ret = readl_poll_timeout(catalog->io->dp_controller.base +
> - MSM_DP_CONTROLLER_LINK_OFFSET +
> + ret = readl_poll_timeout(catalog->io->dp_controller.link +
> REG_DP_MAINLINK_READY,
> data, data & DP_MAINLINK_READY_FOR_VIDEO,
> POLLING_SLEEP_US, POLLING_TIMEOUT_US);
> diff --git a/drivers/gpu/drm/msm/dp/dp_parser.c
> b/drivers/gpu/drm/msm/dp/dp_parser.c
> index 0519dd3ac3c3..51ec85b4803b 100644
> --- a/drivers/gpu/drm/msm/dp/dp_parser.c
> +++ b/drivers/gpu/drm/msm/dp/dp_parser.c
> @@ -250,6 +250,7 @@ static int dp_parser_clock(struct dp_parser
> *parser)
>
> static int dp_parser_parse(struct dp_parser *parser)
> {
> + struct dss_io_data *io = &parser->io.dp_controller;
> int rc = 0;
>
> if (!parser) {
> @@ -275,6 +276,15 @@ static int dp_parser_parse(struct dp_parser
> *parser)
> */
> parser->regulator_cfg = &sdm845_dp_reg_cfg;
>
> + io->ahb = io->base + 0x0;
> + io->ahb_len = 0x200;
> + io->aux = io->base + 0x200;
> + io->aux_len = 0x200;
> + io->link = io->base + 0x400;
> + io->link_len = 0x600;
> + io->p0 = io->base + 0x1000;
> + io->p0_len = 0x400;
> +
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/msm/dp/dp_parser.h
> b/drivers/gpu/drm/msm/dp/dp_parser.h
> index 34b49628bbaf..ff4774109c63 100644
> --- a/drivers/gpu/drm/msm/dp/dp_parser.h
> +++ b/drivers/gpu/drm/msm/dp/dp_parser.h
> @@ -28,6 +28,14 @@ enum dp_pm_type {
> struct dss_io_data {
> u32 len;
> void __iomem *base;
> + void __iomem *ahb;
> + size_t ahb_len;
> + void __iomem *aux;
> + size_t aux_len;
> + void __iomem *link;
> + size_t link_len;
> + void __iomem *p0;
> + size_t p0_len;
> };
>
> static inline const char *dp_parser_pm_name(enum dp_pm_type module)
next prev parent reply other threads:[~2021-05-28 23:15 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-11 4:20 [PATCH 0/4] drm/msm/dp: Add support for SC8180x eDP controller Bjorn Andersson
2021-05-11 4:20 ` Bjorn Andersson
2021-05-11 4:20 ` [PATCH 1/4] drm/msm/dp: Simplify the mvid/nvid calculation Bjorn Andersson
2021-05-11 4:20 ` Bjorn Andersson
2021-05-28 23:11 ` [Freedreno] " abhinavk
2021-05-28 23:11 ` abhinavk
2021-06-08 20:13 ` Bjorn Andersson
2021-06-08 20:13 ` Bjorn Andersson
2021-06-09 0:08 ` abhinavk
2021-06-09 0:08 ` abhinavk
2021-05-11 4:20 ` [PATCH 2/4] drm/msm/dp: Store each subblock in the io region Bjorn Andersson
2021-05-11 4:20 ` Bjorn Andersson
2021-05-28 23:14 ` abhinavk [this message]
2021-05-28 23:14 ` [Freedreno] " abhinavk
2021-05-11 4:20 ` [PATCH 3/4] drm/msm/dp: Initialize the INTF_CONFIG register Bjorn Andersson
2021-05-11 4:20 ` Bjorn Andersson
2021-05-28 23:28 ` [Freedreno] " abhinavk
2021-05-28 23:28 ` abhinavk
2021-05-11 4:20 ` [PATCH 4/4] drm/msm/dp: Add support for SC8180x eDP Bjorn Andersson
2021-05-11 4:20 ` Bjorn Andersson
2021-05-28 23:40 ` [Freedreno] " abhinavk
2021-05-28 23:40 ` abhinavk
2021-05-29 17:09 ` Bjorn Andersson
2021-05-29 17:09 ` Bjorn Andersson
2021-06-04 21:56 ` Stephen Boyd
2021-06-04 21:56 ` Stephen Boyd
2021-05-19 3:41 ` [Freedreno] [PATCH 0/4] drm/msm/dp: Add support for SC8180x eDP controller abhinavk
2021-05-19 3:41 ` abhinavk
2021-05-19 14:51 ` Bjorn Andersson
2021-05-19 14:51 ` Bjorn Andersson
2021-05-28 22:37 ` abhinavk
2021-05-28 22:37 ` abhinavk
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=0a2e38497feb4b6904f5e5bc3ed43c62@codeaurora.org \
--to=abhinavk@codeaurora.org \
--cc=airlied@linux.ie \
--cc=bjorn.andersson@linaro.org \
--cc=chandanu@codeaurora.org \
--cc=daniel@ffwll.ch \
--cc=dmitry.baryshkov@linaro.org \
--cc=dri-devel@lists.freedesktop.org \
--cc=freedreno@lists.freedesktop.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=robdclark@gmail.com \
--cc=sbillaka@codeaurora.org \
--cc=sean@poorly.run \
--cc=swboyd@chromium.org \
--cc=tanmay@codeaurora.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.