Re: [PATCH v5 5/5] PCI: qcom: Add OPP support to scale performance state of power domain

From: Krishna Chaitanya Chundru <quic_krichai@quicinc.com>
To: Viresh Kumar <viresh.kumar@linaro.org>,
	Bjorn Helgaas <helgaas@kernel.org>
Cc: <agross@kernel.org>, <andersson@kernel.org>,
	<konrad.dybcio@linaro.org>, <krzysztof.kozlowski+dt@linaro.org>,
	<conor+dt@kernel.org>, <vireshk@kernel.org>, <nm@ti.com>,
	<sboyd@kernel.org>, <mani@kernel.org>, <lpieralisi@kernel.org>,
	<kw@linux.com>, <robh@kernel.org>, <bhelgaas@google.com>,
	<rafael@kernel.org>, <linux-arm-msm@vger.kernel.org>,
	<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, <linux-pm@vger.kernel.org>,
	<quic_vbadigan@quicinc.com>, <quic_nitegupt@quicinc.com>,
	<quic_skananth@quicinc.com>, <quic_ramkri@quicinc.com>,
	<quic_parass@quicinc.com>
Subject: Re: [PATCH v5 5/5] PCI: qcom: Add OPP support to scale performance state of power domain
Date: Mon, 8 Jan 2024 18:49:13 +0530	[thread overview]
Message-ID: <0ba9f2af-169e-a9a2-9ae4-4c6a70b0a94e@quicinc.com> (raw)
In-Reply-To: <15a98ec0-214b-218b-1e3c-c09f770fce2e@quicinc.com>

On 11/8/2023 8:02 AM, Krishna Chaitanya Chundru wrote:
>
> On 11/3/2023 10:42 AM, Viresh Kumar wrote:
>> On 02-11-23, 07:09, Bjorn Helgaas wrote:
>>> On Thu, Nov 02, 2023 at 11:00:13AM +0530, Viresh Kumar wrote:
>>>> On 01-11-23, 17:17, Bjorn Helgaas wrote:
>>>>> Can you expand "OPP" somewhere so we know what it stands for?  I'm
>>>>> sure everybody knows except me :)
>>>> It is "Operating Performance Points", defined here:
>>>>
>>>> Documentation/power/opp.rst
>>> Thanks; I meant in the subject or commit log of the next revision, of
>>> course.
>> Yeah, I understood that. Krishna shall do it in next version I believe.
>>
> Hi All,
>
> I will do this in my next patch both commit message and ICC voting 
> through OPP
>
> got stuck in some other work, will try to send new series as soon as 
> possible.
>
> - Krishna Chaitanya.
>
Hi Viresh,

Sorry for late response.

We calculate ICC BW voting based up on PCIe speed and PCIe width.

Right now we are adding the opp table based up on PCIe speed.

Each PCIe controller can support multiple lane configurations like x1, 
x2, x4, x8, x16 based up on controller capability.

So for each GEN speed we need  up to 5 entries in OPP table. This will 
make OPP table very long.

It is best to calculate the ICC BW voting in the driver itself and apply 
them through ICC driver.

Let me know your opinion on this.

Thanks & Regards,

Krishna Chaitanya.