From: Lucas Stach <l.stach@pengutronix.de> To: Adam Ford <aford173@gmail.com>, linux-arm-kernel@lists.infradead.org Cc: aford@beaconembedded.com, tharvey@gateworks.com, Rob Herring <robh+dt@kernel.org>, Shawn Guo <shawnguo@kernel.org>, Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix Kernel Team <kernel@pengutronix.de>, Fabio Estevam <festevam@gmail.com>, NXP Linux Team <linux-imx@nxp.com>, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH V4 9/9] arm64: dts: imx8mn: Enable GPU Date: Tue, 14 Dec 2021 10:24:20 +0100 [thread overview] Message-ID: <0c64fff9eedee4e6d9cbd2244d7304236f5dcc8d.camel@pengutronix.de> (raw) In-Reply-To: <20211128131853.15125-10-aford173@gmail.com> Am Sonntag, dem 28.11.2021 um 07:18 -0600 schrieb Adam Ford: > The i.MX8M-Nano features a GC7000. The Etnaviv driver detects it as: > > etnaviv-gpu 38000000.gpu: model: GC7000, revision: 6203 > > Signed-off-by: Adam Ford <aford173@gmail.com> > --- > arch/arm64/boot/dts/freescale/imx8mn.dtsi | 25 +++++++++++++++++++++++ > 1 file changed, 25 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi > index d8726d0ce326..5b8f8488e362 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi > @@ -1117,6 +1117,31 @@ gpmi: nand-controller@33002000 { > status = "disabled"; > }; > > + gpu: gpu@38000000 { > + compatible = "vivante,gc"; > + reg = <0x38000000 0x8000>; > + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX8MN_CLK_GPU_AHB>, > + <&clk IMX8MN_CLK_GPU_BUS_ROOT>, > + <&clk IMX8MN_CLK_GPU_CORE_ROOT>, > + <&clk IMX8MN_CLK_GPU_SHADER>; > + clock-names = "reg", "bus", "core", "shader"; > + assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE>, > + <&clk IMX8MN_CLK_GPU_SHADER>, > + <&clk IMX8MN_CLK_GPU_AXI>, > + <&clk IMX8MN_CLK_GPU_AHB>, > + <&clk IMX8MN_GPU_PLL>, > + <&clk IMX8MN_CLK_GPU_CORE>, > + <&clk IMX8MN_CLK_GPU_SHADER>; This repeated CORE and SHADER clock looks odd. Wouldn't it be possible to avoid this by reordering the assigned-clocks? Regards, Lucas > + assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>, > + <&clk IMX8MN_GPU_PLL_OUT>, > + <&clk IMX8MN_SYS_PLL1_800M>, > + <&clk IMX8MN_SYS_PLL1_800M>; > + assigned-clock-rates = <0>, <0>, <800000000>, <400000000>, <1200000000>, > + <400000000>, <400000000>; > + power-domains = <&pgc_gpumix>; > + }; > + > gic: interrupt-controller@38800000 { > compatible = "arm,gic-v3"; > reg = <0x38800000 0x10000>, > -- > 2.32.0 >
WARNING: multiple messages have this Message-ID (diff)
From: Lucas Stach <l.stach@pengutronix.de> To: Adam Ford <aford173@gmail.com>, linux-arm-kernel@lists.infradead.org Cc: aford@beaconembedded.com, tharvey@gateworks.com, Rob Herring <robh+dt@kernel.org>, Shawn Guo <shawnguo@kernel.org>, Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix Kernel Team <kernel@pengutronix.de>, Fabio Estevam <festevam@gmail.com>, NXP Linux Team <linux-imx@nxp.com>, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH V4 9/9] arm64: dts: imx8mn: Enable GPU Date: Tue, 14 Dec 2021 10:24:20 +0100 [thread overview] Message-ID: <0c64fff9eedee4e6d9cbd2244d7304236f5dcc8d.camel@pengutronix.de> (raw) In-Reply-To: <20211128131853.15125-10-aford173@gmail.com> Am Sonntag, dem 28.11.2021 um 07:18 -0600 schrieb Adam Ford: > The i.MX8M-Nano features a GC7000. The Etnaviv driver detects it as: > > etnaviv-gpu 38000000.gpu: model: GC7000, revision: 6203 > > Signed-off-by: Adam Ford <aford173@gmail.com> > --- > arch/arm64/boot/dts/freescale/imx8mn.dtsi | 25 +++++++++++++++++++++++ > 1 file changed, 25 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi > index d8726d0ce326..5b8f8488e362 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi > @@ -1117,6 +1117,31 @@ gpmi: nand-controller@33002000 { > status = "disabled"; > }; > > + gpu: gpu@38000000 { > + compatible = "vivante,gc"; > + reg = <0x38000000 0x8000>; > + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX8MN_CLK_GPU_AHB>, > + <&clk IMX8MN_CLK_GPU_BUS_ROOT>, > + <&clk IMX8MN_CLK_GPU_CORE_ROOT>, > + <&clk IMX8MN_CLK_GPU_SHADER>; > + clock-names = "reg", "bus", "core", "shader"; > + assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE>, > + <&clk IMX8MN_CLK_GPU_SHADER>, > + <&clk IMX8MN_CLK_GPU_AXI>, > + <&clk IMX8MN_CLK_GPU_AHB>, > + <&clk IMX8MN_GPU_PLL>, > + <&clk IMX8MN_CLK_GPU_CORE>, > + <&clk IMX8MN_CLK_GPU_SHADER>; This repeated CORE and SHADER clock looks odd. Wouldn't it be possible to avoid this by reordering the assigned-clocks? Regards, Lucas > + assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>, > + <&clk IMX8MN_GPU_PLL_OUT>, > + <&clk IMX8MN_SYS_PLL1_800M>, > + <&clk IMX8MN_SYS_PLL1_800M>; > + assigned-clock-rates = <0>, <0>, <800000000>, <400000000>, <1200000000>, > + <400000000>, <400000000>; > + power-domains = <&pgc_gpumix>; > + }; > + > gic: interrupt-controller@38800000 { > compatible = "arm,gic-v3"; > reg = <0x38800000 0x10000>, > -- > 2.32.0 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-12-14 9:24 UTC|newest] Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-11-28 13:18 [PATCH V4 0/9] arm64: imx8mn: Enable more imx8m Nano functions Adam Ford 2021-11-28 13:18 ` Adam Ford 2021-11-28 13:18 ` [PATCH V4 1/9] soc: imx: gpcv2: keep i.MX8MN gpumix bus clock enabled Adam Ford 2021-11-28 13:18 ` Adam Ford 2021-12-14 8:53 ` Lucas Stach 2021-12-14 8:53 ` Lucas Stach 2021-11-28 13:18 ` [PATCH V4 2/9] soc: imx: gpcv2: Add dispmix and mipi domains to imx8mn Adam Ford 2021-11-28 13:18 ` Adam Ford 2021-12-14 8:54 ` Lucas Stach 2021-12-14 8:54 ` Lucas Stach 2021-11-28 13:18 ` [PATCH V4 3/9] dt-bindings: power: imx8mn: add defines for DISP blk-ctrl domains Adam Ford 2021-11-28 13:18 ` Adam Ford 2021-11-28 17:17 ` Rob Herring 2021-11-28 17:17 ` Rob Herring 2021-11-28 18:46 ` Adam Ford 2021-11-28 18:46 ` Adam Ford 2021-12-14 9:11 ` Lucas Stach 2021-12-14 9:11 ` Lucas Stach 2021-11-28 13:18 ` [PATCH V4 4/9] dt-bindings: soc: add binding for i.MX8MN DISP blk-ctrl Adam Ford 2021-11-28 13:18 ` Adam Ford 2021-11-28 23:45 ` Rob Herring 2021-11-28 23:45 ` Rob Herring 2021-12-14 9:15 ` Lucas Stach 2021-12-14 9:15 ` Lucas Stach 2021-11-28 13:18 ` [PATCH V4 5/9] soc: imx: imx8m-blk-ctrl: add " Adam Ford 2021-11-28 13:18 ` Adam Ford 2021-11-28 15:21 ` kernel test robot 2021-11-28 15:21 ` kernel test robot 2021-11-28 16:54 ` kernel test robot 2021-11-28 16:54 ` kernel test robot 2021-12-06 13:05 ` Adam Ford 2021-12-06 13:05 ` Adam Ford 2021-12-14 3:40 ` Adam Ford 2021-12-14 3:40 ` Adam Ford 2021-12-14 9:15 ` Lucas Stach 2021-12-14 9:15 ` Lucas Stach 2021-11-28 13:18 ` [PATCH V4 6/9] arm64: dts: imx8mn: add GPC node Adam Ford 2021-11-28 13:18 ` Adam Ford 2021-12-14 9:17 ` Lucas Stach 2021-12-14 9:17 ` Lucas Stach 2021-11-28 13:18 ` [PATCH V4 7/9] arm64: dts: imx8mn: put USB controller into power-domains Adam Ford 2021-11-28 13:18 ` Adam Ford 2021-11-28 13:18 ` [PATCH V4 8/9] arm64: dts: imx8mn: add DISP blk-ctrl Adam Ford 2021-11-28 13:18 ` Adam Ford 2021-12-14 9:19 ` Lucas Stach 2021-12-14 9:19 ` Lucas Stach 2021-11-28 13:18 ` [PATCH V4 9/9] arm64: dts: imx8mn: Enable GPU Adam Ford 2021-11-28 13:18 ` Adam Ford 2021-12-14 9:24 ` Lucas Stach [this message] 2021-12-14 9:24 ` Lucas Stach 2021-12-14 3:03 ` [PATCH V4 0/9] arm64: imx8mn: Enable more imx8m Nano functions Adam Ford 2021-12-14 3:03 ` Adam Ford 2021-12-14 3:13 ` Shawn Guo 2021-12-14 3:13 ` Shawn Guo
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