Re: [PATCH] drm/i915: Relinquish any fence when changing cache levels

From: Chris Wilson <chris@chris-wilson.co.uk>
To: Eric Anholt <eric@anholt.net>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: Relinquish any fence when changing cache levels
Date: Wed, 13 Apr 2011 17:59:59 +0100	[thread overview]
Message-ID: <0d30dc$lqtgut@orsmga001.jf.intel.com> (raw)
In-Reply-To: <87bp0ahzwn.fsf@pollan.anholt.net>

On Wed, 13 Apr 2011 09:36:08 -0700, Eric Anholt <eric@anholt.net> wrote:
> On Wed, 13 Apr 2011 13:25:40 +0100, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> > This is vital to maintain our contract with the hw for not using fences
> > on snooped memory for older chipsets. It should have no impact
> > other than clearing the fence register (and updating the fence
> > bookkeeping) as any future IO access (page faults or pwrite/pread) will
> > go through the cached CPU domain for older chipsets. On SandyBridge, we
> > incur an extra get_fence() on the rare path that we need to perform
> > detiling through a pagefault (i.e. texture transfers).
> 
> Surely you could just update this to do that for the hardware that
> requires it.  With a comment so someone doesn't delete it later :)

The comment is surely lacking, yes. But the test here for the right
generations is just ugly since losing a CPU fence register is not that
big an issue -- the largest overhead will be in reinstating the vma, and
we need to do that anyway if we mix CPU / GTT reads through the pagefault
handler.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre