Re: [PATCH 6/7] clk: qcom: gcc-ipq9574: Add PCIe related clocks

From: Sricharan Ramabadhran <quic_srichara@quicinc.com>
To: Devi Priya <quic_devipriy@quicinc.com>, <agross@kernel.org>,
	<andersson@kernel.org>, <konrad.dybcio@linaro.org>,
	<lpieralisi@kernel.org>, <kw@linux.com>, <robh@kernel.org>,
	<bhelgaas@google.com>, <krzysztof.kozlowski+dt@linaro.org>,
	<vkoul@kernel.org>, <kishon@kernel.org>,
	<mturquette@baylibre.com>, <sboyd@kernel.org>, <mani@kernel.org>,
	<p.zabel@pengutronix.de>, <svarbanov@mm-sol.com>,
	<linux-arm-msm@vger.kernel.org>, <linux-pci@vger.kernel.org>,
	<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-phy@lists.infradead.org>, <linux-clk@vger.kernel.org>
Cc: <quic_gokulsri@quicinc.com>, <quic_sjaganat@quicinc.com>,
	<quic_kathirav@quicinc.com>, <quic_arajkuma@quicinc.com>,
	<quic_anusha@quicinc.com>
Subject: Re: [PATCH 6/7] clk: qcom: gcc-ipq9574: Add PCIe related clocks
Date: Fri, 17 Feb 2023 14:13:55 +0530	[thread overview]
Message-ID: <0d5f6df8-bb44-f9fe-8d5c-50e488ae4c53@quicinc.com> (raw)
In-Reply-To: <20230214164135.17039-7-quic_devipriy@quicinc.com>

Hi Devi,

On 2/14/2023 10:11 PM, Devi Priya wrote:
> Add the clocks needed for enabling PCIe in IPQ9574
> 
> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
> ---
>   drivers/clk/qcom/gcc-ipq9574.c | 76 ++++++++++++++++++++++++++++++++++
>   1 file changed, 76 insertions(+)
> 
> diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
> index b2a2d618a5ec..1bf33d582dc2 100644
> --- a/drivers/clk/qcom/gcc-ipq9574.c
> +++ b/drivers/clk/qcom/gcc-ipq9574.c
> @@ -1538,6 +1538,24 @@ static struct clk_regmap_phy_mux pcie0_pipe_clk_src = {
>   	},
>   };
>   
> +static struct clk_branch gcc_pcie0_pipe_clk = {
> +	.halt_reg = 0x28044,
> +	.halt_check = BRANCH_HALT_DELAY,
> +	.clkr = {
> +		.enable_reg = 0x28044,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data){
> +			.name = "gcc_pcie0_pipe_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +				&pcie0_pipe_clk_src.clkr.hw
> +			},
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +

   Also, this patch should come before your phy driver updates.

Regards,
  Sricharan