From: Florian Fainelli <f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: Neil Armstrong
<narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>,
khilman-rdvid1DuHRBWk0Htik3J/w@public.gmane.org,
carlo-KA+7E9HrN00dnm+yROfE0A@public.gmane.org,
linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org
Cc: linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
netdev-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [RFC PATCH 09/13] net: phy: Add Meson GXL Internal PHY driver
Date: Fri, 21 Oct 2016 13:56:30 -0700 [thread overview]
Message-ID: <0ea5a7a8-3913-0e6a-6ff2-9f34015ea071@gmail.com> (raw)
In-Reply-To: <1477060838-14164-10-git-send-email-narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
On 10/21/2016 07:40 AM, Neil Armstrong wrote:
> Add driver for the Internal RMII PHY found in the Amlogic Meson GXL SoCs.
>
> This PHY seems to only implement some standard registers and need some
> workarounds to provide autoneg values from vendor registers.
>
> Some magic values are currently used to configure the PHY, and this a
> temporary setup until clarification about these registers names and
> registers fields are provided by Amlogic.
>
> Signed-off-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
> ---
> +
> +static int meson_gxl_config_init(struct phy_device *phydev)
> +{
> + int val;
> + u32 features;
> +
> + meson_gxl_phy_config(phydev);
> +
> + features = SUPPORTED_MII;
This does not really belong in the PHY driver, and this is statically
assigned, I would just drop this.
> +
> + /* Do we support autonegotiation? */
> + val = phy_read(phydev, MII_BMSR);
> + if (val < 0)
> + return val;
> +
> + if (val & BMSR_ANEGCAPABLE)
> + features |= SUPPORTED_Autoneg;
> + if (val & BMSR_100FULL)
> + features |= SUPPORTED_100baseT_Full;
> + if (val & BMSR_100HALF)
> + features |= SUPPORTED_100baseT_Half;
> + if (val & BMSR_10FULL)
> + features |= SUPPORTED_10baseT_Full;
> + if (val & BMSR_10HALF)
> + features |= SUPPORTED_10baseT_Half;
> +
> + phydev->supported = features;
> + phydev->advertising = features;
This is redundant with what PHYLIB will determine for the PHY.
> +
> + return 0;
> +}
> +
> +static int meson_gxl_phy_read_status(struct phy_device *phydev)
> +{
> + int err;
> +
> + /* Update the link, but return if there was an error */
> + err = genphy_update_link(phydev);
> + if (err)
> + return err;
> +
> + phydev->lp_advertising = 0;
> + phydev->pause = 0;
> + phydev->asym_pause = 0;
> +
> + if (phydev->autoneg == AUTONEG_ENABLE) {
> + unsigned int speed;
> + int reg = phy_read(phydev, GXL_REG_ANEG);
Is all of this really necessary? This should all be reflected in the
standard BMSR register, is not this the case here that we have to read
this non-standard register?
You use genphy_config_aneg(), so surely, the standard auto-negotiation
part works somehow?
> +
> + if (reg < 0)
> + return reg;
> +
> + speed = reg & REG_ANEG_SPEED_MASK;
> +
> + if (reg & REG_ANEG_FDUPLEX)
> + phydev->duplex = DUPLEX_FULL;
> + else
> + phydev->duplex = DUPLEX_HALF;
> +
> + if ((reg & REG_ANEG_SPEED_MASK) == REG_ANEG_SPEED10)
> + phydev->speed = SPEED_10;
> + else if ((reg & REG_ANEG_SPEED_MASK) == REG_ANEG_SPEED100)
> + phydev->speed = SPEED_100;
> + } else {
> + int bmcr = phy_read(phydev, MII_BMCR);
> +
> + if (bmcr < 0)
> + return bmcr;
> +
> + if (bmcr & BMCR_FULLDPLX)
> + phydev->duplex = DUPLEX_FULL;
> + else
> + phydev->duplex = DUPLEX_HALF;
> +
> + if (bmcr & BMCR_SPEED1000)
> + phydev->speed = SPEED_1000;
> + else if (bmcr & BMCR_SPEED100)
> + phydev->speed = SPEED_100;
> + else
> + phydev->speed = SPEED_10;
> + }
> +
> + return 0;
> +}
> +
> +static struct phy_driver meson_gxl_phy = {
> + .phy_id = 0x01814400,
> + .name = "Meson GXL Internal PHY",
> + .phy_id_mask = 0x0fffffff,
Usually the last 4 bits are 0, since that's where the revision part is
located.
> + .features = 0,
You should set PHY_GBIT_FEATURES and set .flags to PHY_IS_INTERNAL since
this is an internal PHY?
--
Florian
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WARNING: multiple messages have this Message-ID (diff)
From: Florian Fainelli <f.fainelli@gmail.com>
To: Neil Armstrong <narmstrong@baylibre.com>,
khilman@baylibre.com, carlo@caione.org, linus.walleij@linaro.org
Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org,
netdev@vger.kernel.org
Subject: Re: [RFC PATCH 09/13] net: phy: Add Meson GXL Internal PHY driver
Date: Fri, 21 Oct 2016 13:56:30 -0700 [thread overview]
Message-ID: <0ea5a7a8-3913-0e6a-6ff2-9f34015ea071@gmail.com> (raw)
In-Reply-To: <1477060838-14164-10-git-send-email-narmstrong@baylibre.com>
On 10/21/2016 07:40 AM, Neil Armstrong wrote:
> Add driver for the Internal RMII PHY found in the Amlogic Meson GXL SoCs.
>
> This PHY seems to only implement some standard registers and need some
> workarounds to provide autoneg values from vendor registers.
>
> Some magic values are currently used to configure the PHY, and this a
> temporary setup until clarification about these registers names and
> registers fields are provided by Amlogic.
>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
> ---
> +
> +static int meson_gxl_config_init(struct phy_device *phydev)
> +{
> + int val;
> + u32 features;
> +
> + meson_gxl_phy_config(phydev);
> +
> + features = SUPPORTED_MII;
This does not really belong in the PHY driver, and this is statically
assigned, I would just drop this.
> +
> + /* Do we support autonegotiation? */
> + val = phy_read(phydev, MII_BMSR);
> + if (val < 0)
> + return val;
> +
> + if (val & BMSR_ANEGCAPABLE)
> + features |= SUPPORTED_Autoneg;
> + if (val & BMSR_100FULL)
> + features |= SUPPORTED_100baseT_Full;
> + if (val & BMSR_100HALF)
> + features |= SUPPORTED_100baseT_Half;
> + if (val & BMSR_10FULL)
> + features |= SUPPORTED_10baseT_Full;
> + if (val & BMSR_10HALF)
> + features |= SUPPORTED_10baseT_Half;
> +
> + phydev->supported = features;
> + phydev->advertising = features;
This is redundant with what PHYLIB will determine for the PHY.
> +
> + return 0;
> +}
> +
> +static int meson_gxl_phy_read_status(struct phy_device *phydev)
> +{
> + int err;
> +
> + /* Update the link, but return if there was an error */
> + err = genphy_update_link(phydev);
> + if (err)
> + return err;
> +
> + phydev->lp_advertising = 0;
> + phydev->pause = 0;
> + phydev->asym_pause = 0;
> +
> + if (phydev->autoneg == AUTONEG_ENABLE) {
> + unsigned int speed;
> + int reg = phy_read(phydev, GXL_REG_ANEG);
Is all of this really necessary? This should all be reflected in the
standard BMSR register, is not this the case here that we have to read
this non-standard register?
You use genphy_config_aneg(), so surely, the standard auto-negotiation
part works somehow?
> +
> + if (reg < 0)
> + return reg;
> +
> + speed = reg & REG_ANEG_SPEED_MASK;
> +
> + if (reg & REG_ANEG_FDUPLEX)
> + phydev->duplex = DUPLEX_FULL;
> + else
> + phydev->duplex = DUPLEX_HALF;
> +
> + if ((reg & REG_ANEG_SPEED_MASK) == REG_ANEG_SPEED10)
> + phydev->speed = SPEED_10;
> + else if ((reg & REG_ANEG_SPEED_MASK) == REG_ANEG_SPEED100)
> + phydev->speed = SPEED_100;
> + } else {
> + int bmcr = phy_read(phydev, MII_BMCR);
> +
> + if (bmcr < 0)
> + return bmcr;
> +
> + if (bmcr & BMCR_FULLDPLX)
> + phydev->duplex = DUPLEX_FULL;
> + else
> + phydev->duplex = DUPLEX_HALF;
> +
> + if (bmcr & BMCR_SPEED1000)
> + phydev->speed = SPEED_1000;
> + else if (bmcr & BMCR_SPEED100)
> + phydev->speed = SPEED_100;
> + else
> + phydev->speed = SPEED_10;
> + }
> +
> + return 0;
> +}
> +
> +static struct phy_driver meson_gxl_phy = {
> + .phy_id = 0x01814400,
> + .name = "Meson GXL Internal PHY",
> + .phy_id_mask = 0x0fffffff,
Usually the last 4 bits are 0, since that's where the revision part is
located.
> + .features = 0,
You should set PHY_GBIT_FEATURES and set .flags to PHY_IS_INTERNAL since
this is an internal PHY?
--
Florian
WARNING: multiple messages have this Message-ID (diff)
From: f.fainelli@gmail.com (Florian Fainelli)
To: linux-arm-kernel@lists.infradead.org
Subject: [RFC PATCH 09/13] net: phy: Add Meson GXL Internal PHY driver
Date: Fri, 21 Oct 2016 13:56:30 -0700 [thread overview]
Message-ID: <0ea5a7a8-3913-0e6a-6ff2-9f34015ea071@gmail.com> (raw)
In-Reply-To: <1477060838-14164-10-git-send-email-narmstrong@baylibre.com>
On 10/21/2016 07:40 AM, Neil Armstrong wrote:
> Add driver for the Internal RMII PHY found in the Amlogic Meson GXL SoCs.
>
> This PHY seems to only implement some standard registers and need some
> workarounds to provide autoneg values from vendor registers.
>
> Some magic values are currently used to configure the PHY, and this a
> temporary setup until clarification about these registers names and
> registers fields are provided by Amlogic.
>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
> ---
> +
> +static int meson_gxl_config_init(struct phy_device *phydev)
> +{
> + int val;
> + u32 features;
> +
> + meson_gxl_phy_config(phydev);
> +
> + features = SUPPORTED_MII;
This does not really belong in the PHY driver, and this is statically
assigned, I would just drop this.
> +
> + /* Do we support autonegotiation? */
> + val = phy_read(phydev, MII_BMSR);
> + if (val < 0)
> + return val;
> +
> + if (val & BMSR_ANEGCAPABLE)
> + features |= SUPPORTED_Autoneg;
> + if (val & BMSR_100FULL)
> + features |= SUPPORTED_100baseT_Full;
> + if (val & BMSR_100HALF)
> + features |= SUPPORTED_100baseT_Half;
> + if (val & BMSR_10FULL)
> + features |= SUPPORTED_10baseT_Full;
> + if (val & BMSR_10HALF)
> + features |= SUPPORTED_10baseT_Half;
> +
> + phydev->supported = features;
> + phydev->advertising = features;
This is redundant with what PHYLIB will determine for the PHY.
> +
> + return 0;
> +}
> +
> +static int meson_gxl_phy_read_status(struct phy_device *phydev)
> +{
> + int err;
> +
> + /* Update the link, but return if there was an error */
> + err = genphy_update_link(phydev);
> + if (err)
> + return err;
> +
> + phydev->lp_advertising = 0;
> + phydev->pause = 0;
> + phydev->asym_pause = 0;
> +
> + if (phydev->autoneg == AUTONEG_ENABLE) {
> + unsigned int speed;
> + int reg = phy_read(phydev, GXL_REG_ANEG);
Is all of this really necessary? This should all be reflected in the
standard BMSR register, is not this the case here that we have to read
this non-standard register?
You use genphy_config_aneg(), so surely, the standard auto-negotiation
part works somehow?
> +
> + if (reg < 0)
> + return reg;
> +
> + speed = reg & REG_ANEG_SPEED_MASK;
> +
> + if (reg & REG_ANEG_FDUPLEX)
> + phydev->duplex = DUPLEX_FULL;
> + else
> + phydev->duplex = DUPLEX_HALF;
> +
> + if ((reg & REG_ANEG_SPEED_MASK) == REG_ANEG_SPEED10)
> + phydev->speed = SPEED_10;
> + else if ((reg & REG_ANEG_SPEED_MASK) == REG_ANEG_SPEED100)
> + phydev->speed = SPEED_100;
> + } else {
> + int bmcr = phy_read(phydev, MII_BMCR);
> +
> + if (bmcr < 0)
> + return bmcr;
> +
> + if (bmcr & BMCR_FULLDPLX)
> + phydev->duplex = DUPLEX_FULL;
> + else
> + phydev->duplex = DUPLEX_HALF;
> +
> + if (bmcr & BMCR_SPEED1000)
> + phydev->speed = SPEED_1000;
> + else if (bmcr & BMCR_SPEED100)
> + phydev->speed = SPEED_100;
> + else
> + phydev->speed = SPEED_10;
> + }
> +
> + return 0;
> +}
> +
> +static struct phy_driver meson_gxl_phy = {
> + .phy_id = 0x01814400,
> + .name = "Meson GXL Internal PHY",
> + .phy_id_mask = 0x0fffffff,
Usually the last 4 bits are 0, since that's where the revision part is
located.
> + .features = 0,
You should set PHY_GBIT_FEATURES and set .flags to PHY_IS_INTERNAL since
this is an internal PHY?
--
Florian
WARNING: multiple messages have this Message-ID (diff)
From: f.fainelli@gmail.com (Florian Fainelli)
To: linus-amlogic@lists.infradead.org
Subject: [RFC PATCH 09/13] net: phy: Add Meson GXL Internal PHY driver
Date: Fri, 21 Oct 2016 13:56:30 -0700 [thread overview]
Message-ID: <0ea5a7a8-3913-0e6a-6ff2-9f34015ea071@gmail.com> (raw)
In-Reply-To: <1477060838-14164-10-git-send-email-narmstrong@baylibre.com>
On 10/21/2016 07:40 AM, Neil Armstrong wrote:
> Add driver for the Internal RMII PHY found in the Amlogic Meson GXL SoCs.
>
> This PHY seems to only implement some standard registers and need some
> workarounds to provide autoneg values from vendor registers.
>
> Some magic values are currently used to configure the PHY, and this a
> temporary setup until clarification about these registers names and
> registers fields are provided by Amlogic.
>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
> ---
> +
> +static int meson_gxl_config_init(struct phy_device *phydev)
> +{
> + int val;
> + u32 features;
> +
> + meson_gxl_phy_config(phydev);
> +
> + features = SUPPORTED_MII;
This does not really belong in the PHY driver, and this is statically
assigned, I would just drop this.
> +
> + /* Do we support autonegotiation? */
> + val = phy_read(phydev, MII_BMSR);
> + if (val < 0)
> + return val;
> +
> + if (val & BMSR_ANEGCAPABLE)
> + features |= SUPPORTED_Autoneg;
> + if (val & BMSR_100FULL)
> + features |= SUPPORTED_100baseT_Full;
> + if (val & BMSR_100HALF)
> + features |= SUPPORTED_100baseT_Half;
> + if (val & BMSR_10FULL)
> + features |= SUPPORTED_10baseT_Full;
> + if (val & BMSR_10HALF)
> + features |= SUPPORTED_10baseT_Half;
> +
> + phydev->supported = features;
> + phydev->advertising = features;
This is redundant with what PHYLIB will determine for the PHY.
> +
> + return 0;
> +}
> +
> +static int meson_gxl_phy_read_status(struct phy_device *phydev)
> +{
> + int err;
> +
> + /* Update the link, but return if there was an error */
> + err = genphy_update_link(phydev);
> + if (err)
> + return err;
> +
> + phydev->lp_advertising = 0;
> + phydev->pause = 0;
> + phydev->asym_pause = 0;
> +
> + if (phydev->autoneg == AUTONEG_ENABLE) {
> + unsigned int speed;
> + int reg = phy_read(phydev, GXL_REG_ANEG);
Is all of this really necessary? This should all be reflected in the
standard BMSR register, is not this the case here that we have to read
this non-standard register?
You use genphy_config_aneg(), so surely, the standard auto-negotiation
part works somehow?
> +
> + if (reg < 0)
> + return reg;
> +
> + speed = reg & REG_ANEG_SPEED_MASK;
> +
> + if (reg & REG_ANEG_FDUPLEX)
> + phydev->duplex = DUPLEX_FULL;
> + else
> + phydev->duplex = DUPLEX_HALF;
> +
> + if ((reg & REG_ANEG_SPEED_MASK) == REG_ANEG_SPEED10)
> + phydev->speed = SPEED_10;
> + else if ((reg & REG_ANEG_SPEED_MASK) == REG_ANEG_SPEED100)
> + phydev->speed = SPEED_100;
> + } else {
> + int bmcr = phy_read(phydev, MII_BMCR);
> +
> + if (bmcr < 0)
> + return bmcr;
> +
> + if (bmcr & BMCR_FULLDPLX)
> + phydev->duplex = DUPLEX_FULL;
> + else
> + phydev->duplex = DUPLEX_HALF;
> +
> + if (bmcr & BMCR_SPEED1000)
> + phydev->speed = SPEED_1000;
> + else if (bmcr & BMCR_SPEED100)
> + phydev->speed = SPEED_100;
> + else
> + phydev->speed = SPEED_10;
> + }
> +
> + return 0;
> +}
> +
> +static struct phy_driver meson_gxl_phy = {
> + .phy_id = 0x01814400,
> + .name = "Meson GXL Internal PHY",
> + .phy_id_mask = 0x0fffffff,
Usually the last 4 bits are 0, since that's where the revision part is
located.
> + .features = 0,
You should set PHY_GBIT_FEATURES and set .flags to PHY_IS_INTERNAL since
this is an internal PHY?
--
Florian
next prev parent reply other threads:[~2016-10-21 20:56 UTC|newest]
Thread overview: 84+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-21 14:40 [RFC PATCH 00/13] ARM64: meson-gxl: Add extended support Neil Armstrong
2016-10-21 14:40 ` Neil Armstrong
2016-10-21 14:40 ` Neil Armstrong
[not found] ` <1477060838-14164-1-git-send-email-narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
2016-10-21 14:40 ` [RFC PATCH 01/13] pinctrl: meson: Add GXL pinctrl definitions Neil Armstrong
2016-10-21 14:40 ` Neil Armstrong
2016-10-21 14:40 ` Neil Armstrong
2016-10-21 14:40 ` Neil Armstrong
[not found] ` <1477060838-14164-2-git-send-email-narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
2016-10-24 1:03 ` Linus Walleij
2016-10-24 1:03 ` Linus Walleij
2016-10-24 1:03 ` Linus Walleij
2016-10-24 1:03 ` Linus Walleij
2016-10-31 9:40 ` Neil Armstrong
2016-10-31 9:40 ` Neil Armstrong
2016-10-31 9:40 ` Neil Armstrong
2016-10-31 9:40 ` Neil Armstrong
[not found] ` <b80010f7-196a-abeb-e4a2-5009f3b7f13b-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
2016-10-31 18:23 ` Kevin Hilman
2016-10-31 18:23 ` Kevin Hilman
2016-10-31 18:23 ` Kevin Hilman
2016-10-31 18:23 ` Kevin Hilman
2016-10-31 18:23 ` Kevin Hilman
2016-10-30 20:41 ` Rob Herring
2016-10-30 20:41 ` Rob Herring
2016-10-30 20:41 ` Rob Herring
2016-10-21 14:40 ` [RFC PATCH 02/13] ARM64: dts: meson-gxbb: Move common nodes to meson-gx Neil Armstrong
2016-10-21 14:40 ` Neil Armstrong
2016-10-21 14:40 ` Neil Armstrong
2016-10-21 14:40 ` Neil Armstrong
2016-10-21 14:40 ` [RFC PATCH 03/13] ARM64: dts: meson-gxl: Add pinctrl nodes Neil Armstrong
2016-10-21 14:40 ` Neil Armstrong
2016-10-21 14:40 ` Neil Armstrong
2016-10-21 14:40 ` [RFC PATCH 04/13] ARM64: dts: meson-gxl: Add clock nodes Neil Armstrong
2016-10-21 14:40 ` Neil Armstrong
2016-10-21 14:40 ` Neil Armstrong
2016-10-21 14:40 ` [RFC PATCH 05/13] ARM64: dts: meson-gxl: Add i2c nodes Neil Armstrong
2016-10-21 14:40 ` Neil Armstrong
2016-10-21 14:40 ` Neil Armstrong
2016-10-21 14:40 ` [RFC PATCH 06/13] ARM64: dts: meson-gxl: Add MMC/SD/SDIO nodes Neil Armstrong
2016-10-21 14:40 ` Neil Armstrong
2016-10-21 14:40 ` Neil Armstrong
2016-10-21 14:40 ` [RFC PATCH 07/13] ARM64: dts: meson-gxl-p23x: Add uart pinctrl Neil Armstrong
2016-10-21 14:40 ` Neil Armstrong
2016-10-21 14:40 ` Neil Armstrong
2016-10-21 14:40 ` Neil Armstrong
2016-10-21 14:40 ` [RFC PATCH 08/13] dwmac-meson8b: add support for phy selection Neil Armstrong
2016-10-21 14:40 ` Neil Armstrong
2016-10-21 14:40 ` Neil Armstrong
2016-10-21 15:46 ` Andrew Lunn
2016-10-21 15:46 ` Andrew Lunn
2016-10-21 15:46 ` Andrew Lunn
2016-10-21 15:54 ` Andrew Lunn
2016-10-21 15:54 ` Andrew Lunn
2016-10-21 15:54 ` Andrew Lunn
2016-10-21 15:59 ` Neil Armstrong
2016-10-21 15:59 ` Neil Armstrong
2016-10-21 15:59 ` Neil Armstrong
2016-10-21 16:08 ` Andrew Lunn
2016-10-21 16:08 ` Andrew Lunn
2016-10-21 16:08 ` Andrew Lunn
2016-10-31 14:23 ` Neil Armstrong
2016-10-31 14:23 ` Neil Armstrong
2016-10-31 14:23 ` Neil Armstrong
2016-10-21 14:40 ` [RFC PATCH 09/13] net: phy: Add Meson GXL Internal PHY driver Neil Armstrong
2016-10-21 14:40 ` Neil Armstrong
2016-10-21 14:40 ` Neil Armstrong
[not found] ` <1477060838-14164-10-git-send-email-narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
2016-10-21 20:56 ` Florian Fainelli [this message]
2016-10-21 20:56 ` Florian Fainelli
2016-10-21 20:56 ` Florian Fainelli
2016-10-21 20:56 ` Florian Fainelli
[not found] ` <0ea5a7a8-3913-0e6a-6ff2-9f34015ea071-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2016-10-31 14:25 ` Neil Armstrong
2016-10-31 14:25 ` Neil Armstrong
2016-10-31 14:25 ` Neil Armstrong
2016-10-31 14:25 ` Neil Armstrong
2016-10-21 14:40 ` [RFC PATCH 10/13] ARM64: dts: meson-gxl: Add ethernet nodes with internal PHY Neil Armstrong
2016-10-21 14:40 ` Neil Armstrong
2016-10-21 14:40 ` Neil Armstrong
2016-10-21 14:40 ` [RFC PATCH 11/13] ARM64: dts: meson-gxl-p23x: Enable ethernet Neil Armstrong
2016-10-21 14:40 ` Neil Armstrong
2016-10-21 14:40 ` Neil Armstrong
2016-10-21 14:40 ` [RFC PATCH 12/13] ARM64: dts: meson-gxl-p23x: Add SD/SDIO/MMC and PWM nodes Neil Armstrong
2016-10-21 14:40 ` Neil Armstrong
2016-10-21 14:40 ` Neil Armstrong
2016-10-21 14:40 ` [RFC PATCH 13/13] ARM64: dts: meson-gxl-p23x: Enable IR receiver Neil Armstrong
2016-10-21 14:40 ` Neil Armstrong
2016-10-21 14:40 ` Neil Armstrong
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