From: Alexander Stein <alexander.stein@ew.tq-group.com> To: Marek Vasut <marex@denx.de> Cc: linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Adam Ford <aford173@gmail.com>, Alice Guo <alice.guo@nxp.com>, Amit Kucheria <amitk@kernel.org>, Daniel Lezcano <daniel.lezcano@linaro.org>, Fabio Estevam <festevam@gmail.com>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Li Jun <jun.li@nxp.com>, Lucas Stach <l.stach@pengutronix.de>, Markus Niebel <Markus.Niebel@ew.tq-group.com>, NXP Linux Team <linux-imx@nxp.com>, Peng Fan <peng.fan@nxp.com>, Pengutronix Kernel Team <kernel@pengutronix.de>, "Rafael J . Wysocki" <rafael@kernel.org>, Richard Cochran <richardcochran@gmail.com>, Rob Herring <robh+dt@kernel.org>, Sascha Hauer <s.hauer@pengutronix.de>, Shawn Guo <shawnguo@kernel.org>, Zhang Rui <rui.zhang@intel.com>, devicetree@vger.kernel.org, Marek Vasut <marex@denx.de> Subject: Re: [PATCH 4/5] arm64: dts: imx8m: Add TMU phandle to calibration data in OCOTP Date: Mon, 28 Nov 2022 09:34:03 +0100 [thread overview] Message-ID: <12103021.O9o76ZdvQC@steina-w> (raw) In-Reply-To: <20221126224740.311625-4-marex@denx.de> Hi Marek, Am Samstag, 26. November 2022, 23:47:39 CET schrieb Marek Vasut: > The TMU TASR, TCALIVn, TRIM registers must be explicitly programmed with > calibration values in OCOTP. Add the OCOTP calibration values phandle so > the TMU driver can perform this programming. > > The MX8MM/MX8MN TMUv1 uses only one OCOTP cell, while MX8MP TMUv2 uses 4. Is there any source for the fuse addresses? I can only find OCOTP_OCOTP_HW_OCOTP_ANA1 and a calibration description in TMU section in the IMX8MNRM Rev 2, but I can't find any fuse for imx8mm and imx8mp. Best regards, Alexander > Signed-off-by: Marek Vasut <marex@denx.de> > --- > Cc: Adam Ford <aford173@gmail.com> > Cc: Alice Guo <alice.guo@nxp.com> > Cc: Amit Kucheria <amitk@kernel.org> > Cc: Daniel Lezcano <daniel.lezcano@linaro.org> > Cc: Fabio Estevam <festevam@gmail.com> > Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> > Cc: Li Jun <jun.li@nxp.com> > Cc: Lucas Stach <l.stach@pengutronix.de> > Cc: Markus Niebel <Markus.Niebel@ew.tq-group.com> > Cc: NXP Linux Team <linux-imx@nxp.com> > Cc: Peng Fan <peng.fan@nxp.com> > Cc: Pengutronix Kernel Team <kernel@pengutronix.de> > Cc: Rafael J. Wysocki <rafael@kernel.org> > Cc: Richard Cochran <richardcochran@gmail.com> > Cc: Rob Herring <robh+dt@kernel.org> > Cc: Sascha Hauer <s.hauer@pengutronix.de> > Cc: Shawn Guo <shawnguo@kernel.org> > Cc: Zhang Rui <rui.zhang@intel.com> > Cc: devicetree@vger.kernel.org > To: linux-pm@vger.kernel.org > To: linux-arm-kernel@lists.infradead.org > --- > arch/arm64/boot/dts/freescale/imx8mm.dtsi | 6 ++++++ > arch/arm64/boot/dts/freescale/imx8mn.dtsi | 6 ++++++ > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 6 ++++++ > 3 files changed, 18 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi > b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index > 513c2de0caa15..0cd7fff47c44d 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > @@ -496,6 +496,8 @@ tmu: tmu@30260000 { > compatible = "fsl,imx8mm-tmu"; > reg = <0x30260000 0x10000>; > clocks = <&clk IMX8MM_CLK_TMU_ROOT>; > + nvmem-cells = <&tmu_calib>; > + nvmem-cell-names = "calib"; > #thermal-sensor-cells = <0>; > }; > > @@ -584,6 +586,10 @@ cpu_speed_grade: speed-grade@10 { /* 0x440 */ > reg = <0x10 4>; > }; > > + tmu_calib: calib@3c { /* 0x4f0 */ > + reg = <0x3c 4>; > + }; > + > fec_mac_address: mac-address@90 { /* 0x640 */ > reg = <0x90 6>; > }; > diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi > b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index > 068f599cdf757..5eef9b274edde 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi > @@ -498,6 +498,8 @@ tmu: tmu@30260000 { > compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu"; > reg = <0x30260000 0x10000>; > clocks = <&clk IMX8MN_CLK_TMU_ROOT>; > + nvmem-cells = <&tmu_calib>; > + nvmem-cell-names = "calib"; > #thermal-sensor-cells = <0>; > }; > > @@ -585,6 +587,10 @@ cpu_speed_grade: speed-grade@10 { /* 0x440 */ > reg = <0x10 4>; > }; > > + tmu_calib: calib@3c { /* 0x4f0 */ > + reg = <0x3c 4>; > + }; > + > fec_mac_address: mac-address@90 { /* 0x640 */ > reg = <0x90 6>; > }; > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index > ddcd5e23ba47d..0173e394ad4d8 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > @@ -380,6 +380,8 @@ tmu: tmu@30260000 { > compatible = "fsl,imx8mp-tmu"; > reg = <0x30260000 0x10000>; > clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>; > + nvmem-cells = <&tmu_calib>; > + nvmem-cell-names = "calib"; > #thermal-sensor-cells = <1>; > }; > > @@ -454,6 +456,10 @@ eth_mac1: mac-address@90 { /* 0x640 */ > eth_mac2: mac-address@96 { /* 0x658 */ > reg = <0x96 6>; > }; > + > + tmu_calib: calib@264 { /* 0xd90-0xdc0 */ > + reg = <0x264 0x10>; > + }; > }; > > anatop: clock-controller@30360000 {
WARNING: multiple messages have this Message-ID (diff)
From: Alexander Stein <alexander.stein@ew.tq-group.com> To: Marek Vasut <marex@denx.de> Cc: linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Adam Ford <aford173@gmail.com>, Alice Guo <alice.guo@nxp.com>, Amit Kucheria <amitk@kernel.org>, Daniel Lezcano <daniel.lezcano@linaro.org>, Fabio Estevam <festevam@gmail.com>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Li Jun <jun.li@nxp.com>, Lucas Stach <l.stach@pengutronix.de>, Markus Niebel <Markus.Niebel@ew.tq-group.com>, NXP Linux Team <linux-imx@nxp.com>, Peng Fan <peng.fan@nxp.com>, Pengutronix Kernel Team <kernel@pengutronix.de>, "Rafael J . Wysocki" <rafael@kernel.org>, Richard Cochran <richardcochran@gmail.com>, Rob Herring <robh+dt@kernel.org>, Sascha Hauer <s.hauer@pengutronix.de>, Shawn Guo <shawnguo@kernel.org>, Zhang Rui <rui.zhang@intel.com>, devicetree@vger.kernel.org, Marek Vasut <marex@denx.de> Subject: Re: [PATCH 4/5] arm64: dts: imx8m: Add TMU phandle to calibration data in OCOTP Date: Mon, 28 Nov 2022 09:34:03 +0100 [thread overview] Message-ID: <12103021.O9o76ZdvQC@steina-w> (raw) In-Reply-To: <20221126224740.311625-4-marex@denx.de> Hi Marek, Am Samstag, 26. November 2022, 23:47:39 CET schrieb Marek Vasut: > The TMU TASR, TCALIVn, TRIM registers must be explicitly programmed with > calibration values in OCOTP. Add the OCOTP calibration values phandle so > the TMU driver can perform this programming. > > The MX8MM/MX8MN TMUv1 uses only one OCOTP cell, while MX8MP TMUv2 uses 4. Is there any source for the fuse addresses? I can only find OCOTP_OCOTP_HW_OCOTP_ANA1 and a calibration description in TMU section in the IMX8MNRM Rev 2, but I can't find any fuse for imx8mm and imx8mp. Best regards, Alexander > Signed-off-by: Marek Vasut <marex@denx.de> > --- > Cc: Adam Ford <aford173@gmail.com> > Cc: Alice Guo <alice.guo@nxp.com> > Cc: Amit Kucheria <amitk@kernel.org> > Cc: Daniel Lezcano <daniel.lezcano@linaro.org> > Cc: Fabio Estevam <festevam@gmail.com> > Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> > Cc: Li Jun <jun.li@nxp.com> > Cc: Lucas Stach <l.stach@pengutronix.de> > Cc: Markus Niebel <Markus.Niebel@ew.tq-group.com> > Cc: NXP Linux Team <linux-imx@nxp.com> > Cc: Peng Fan <peng.fan@nxp.com> > Cc: Pengutronix Kernel Team <kernel@pengutronix.de> > Cc: Rafael J. Wysocki <rafael@kernel.org> > Cc: Richard Cochran <richardcochran@gmail.com> > Cc: Rob Herring <robh+dt@kernel.org> > Cc: Sascha Hauer <s.hauer@pengutronix.de> > Cc: Shawn Guo <shawnguo@kernel.org> > Cc: Zhang Rui <rui.zhang@intel.com> > Cc: devicetree@vger.kernel.org > To: linux-pm@vger.kernel.org > To: linux-arm-kernel@lists.infradead.org > --- > arch/arm64/boot/dts/freescale/imx8mm.dtsi | 6 ++++++ > arch/arm64/boot/dts/freescale/imx8mn.dtsi | 6 ++++++ > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 6 ++++++ > 3 files changed, 18 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi > b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index > 513c2de0caa15..0cd7fff47c44d 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > @@ -496,6 +496,8 @@ tmu: tmu@30260000 { > compatible = "fsl,imx8mm-tmu"; > reg = <0x30260000 0x10000>; > clocks = <&clk IMX8MM_CLK_TMU_ROOT>; > + nvmem-cells = <&tmu_calib>; > + nvmem-cell-names = "calib"; > #thermal-sensor-cells = <0>; > }; > > @@ -584,6 +586,10 @@ cpu_speed_grade: speed-grade@10 { /* 0x440 */ > reg = <0x10 4>; > }; > > + tmu_calib: calib@3c { /* 0x4f0 */ > + reg = <0x3c 4>; > + }; > + > fec_mac_address: mac-address@90 { /* 0x640 */ > reg = <0x90 6>; > }; > diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi > b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index > 068f599cdf757..5eef9b274edde 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi > @@ -498,6 +498,8 @@ tmu: tmu@30260000 { > compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu"; > reg = <0x30260000 0x10000>; > clocks = <&clk IMX8MN_CLK_TMU_ROOT>; > + nvmem-cells = <&tmu_calib>; > + nvmem-cell-names = "calib"; > #thermal-sensor-cells = <0>; > }; > > @@ -585,6 +587,10 @@ cpu_speed_grade: speed-grade@10 { /* 0x440 */ > reg = <0x10 4>; > }; > > + tmu_calib: calib@3c { /* 0x4f0 */ > + reg = <0x3c 4>; > + }; > + > fec_mac_address: mac-address@90 { /* 0x640 */ > reg = <0x90 6>; > }; > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index > ddcd5e23ba47d..0173e394ad4d8 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > @@ -380,6 +380,8 @@ tmu: tmu@30260000 { > compatible = "fsl,imx8mp-tmu"; > reg = <0x30260000 0x10000>; > clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>; > + nvmem-cells = <&tmu_calib>; > + nvmem-cell-names = "calib"; > #thermal-sensor-cells = <1>; > }; > > @@ -454,6 +456,10 @@ eth_mac1: mac-address@90 { /* 0x640 */ > eth_mac2: mac-address@96 { /* 0x658 */ > reg = <0x96 6>; > }; > + > + tmu_calib: calib@264 { /* 0xd90-0xdc0 */ > + reg = <0x264 0x10>; > + }; > }; > > anatop: clock-controller@30360000 { _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-11-28 8:34 UTC|newest] Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-11-26 22:47 [PATCH 1/5] dt-bindings: thermal: imx8mm-thermal: Document optional nvmem-cells Marek Vasut 2022-11-26 22:47 ` Marek Vasut 2022-11-26 22:47 ` [PATCH 2/5] arm64: dts: imx8m: Align SoC unique ID node unit address Marek Vasut 2022-11-26 22:47 ` Marek Vasut 2022-11-28 2:16 ` Peng Fan 2022-11-28 2:16 ` Peng Fan 2022-11-26 22:47 ` [PATCH 3/5] arm64: dts: imx8m: Document the fuse address calculation Marek Vasut 2022-11-26 22:47 ` Marek Vasut 2022-11-28 2:18 ` Peng Fan 2022-11-28 2:18 ` Peng Fan 2022-11-26 22:47 ` [PATCH 4/5] arm64: dts: imx8m: Add TMU phandle to calibration data in OCOTP Marek Vasut 2022-11-26 22:47 ` Marek Vasut 2022-11-28 2:29 ` Peng Fan 2022-11-28 2:29 ` Peng Fan 2022-11-28 8:34 ` Alexander Stein [this message] 2022-11-28 8:34 ` Alexander Stein 2022-11-28 9:35 ` Marek Vasut 2022-11-28 9:35 ` Marek Vasut 2022-11-26 22:47 ` [PATCH 5/5] thermal/drivers/imx: Add support for loading calibration data from OCOTP Marek Vasut 2022-11-26 22:47 ` Marek Vasut 2022-11-27 5:07 ` kernel test robot 2022-11-28 2:58 ` Peng Fan 2022-11-28 2:58 ` Peng Fan 2022-11-30 15:14 ` kernel test robot 2022-12-01 5:13 ` kernel test robot 2022-11-27 12:33 ` [PATCH 1/5] dt-bindings: thermal: imx8mm-thermal: Document optional nvmem-cells Krzysztof Kozlowski 2022-11-27 12:33 ` Krzysztof Kozlowski
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