From: Mark Salter <msalter@redhat.com>
To: Grant Likely <grant.likely@secretlab.ca>
Cc: linux-kernel@vger.kernel.org, devicetree-discuss@lists.ozlabs.org
Subject: Re: [PATCH 06/24] C6X: devicetree
Date: Mon, 12 Sep 2011 19:20:35 -0400 [thread overview]
Message-ID: <1315869636.11280.26.camel@deneb.redhat.com> (raw)
In-Reply-To: <20110912201102.GF23345@ponder.secretlab.ca>
On Mon, 2011-09-12 at 14:11 -0600, Grant Likely wrote:
> On Wed, Aug 31, 2011 at 05:26:41PM -0400, Mark Salter wrote:
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + compatible = "ti,c64x+core-pic";
>
> The interrupt controller isn't addressable? Is it integrated into
> the CPU?
Yes, that core controller is controlled through registers accessed
with special-purpose instructions, not MMIO. Other controllers, like
megamodule and some as-yet unimplemented use MMIO.
>
> > + };
> > +
> > + soc@00000000 {
>
> "soc@2a80000" to match the 'reg' property of this node.
Okay, I think I need a separate node for that reg property. The SoC
address space does actually start at 0. The registers in that reg
property are "SoC-level" registers holding silicon revision, pin
strap status, etc. All of the SoCs have a "device state config"
node which have registers like that. Instead of having them in the
device state block, this SoC has them in a separate area. I just
got lazy and put them the reg property in the soc node, but I think
it really calls for a separate node.
--Mark
WARNING: multiple messages have this Message-ID (diff)
From: Mark Salter <msalter-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
To: Grant Likely <grant.likely-s3s/WqlpOiPyB63q8FvJNQ@public.gmane.org>
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH 06/24] C6X: devicetree
Date: Mon, 12 Sep 2011 19:20:35 -0400 [thread overview]
Message-ID: <1315869636.11280.26.camel@deneb.redhat.com> (raw)
In-Reply-To: <20110912201102.GF23345-e0URQFbLeQY2iJbIjFUEsiwD8/FfD2ys@public.gmane.org>
On Mon, 2011-09-12 at 14:11 -0600, Grant Likely wrote:
> On Wed, Aug 31, 2011 at 05:26:41PM -0400, Mark Salter wrote:
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + compatible = "ti,c64x+core-pic";
>
> The interrupt controller isn't addressable? Is it integrated into
> the CPU?
Yes, that core controller is controlled through registers accessed
with special-purpose instructions, not MMIO. Other controllers, like
megamodule and some as-yet unimplemented use MMIO.
>
> > + };
> > +
> > + soc@00000000 {
>
> "soc@2a80000" to match the 'reg' property of this node.
Okay, I think I need a separate node for that reg property. The SoC
address space does actually start at 0. The registers in that reg
property are "SoC-level" registers holding silicon revision, pin
strap status, etc. All of the SoCs have a "device state config"
node which have registers like that. Instead of having them in the
device state block, this SoC has them in a separate area. I just
got lazy and put them the reg property in the soc node, but I think
it really calls for a separate node.
--Mark
next prev parent reply other threads:[~2011-09-12 23:20 UTC|newest]
Thread overview: 92+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-08-31 21:26 [PATCH v2 00/24] C6X: New architecture patch set Mark Salter
2011-08-31 21:26 ` Mark Salter
2011-08-31 21:26 ` [PATCH 01/24] fix default __strnlen_user macro Mark Salter
2011-08-31 21:26 ` Mark Salter
2011-08-31 23:30 ` Ryan Mallon
2011-08-31 23:30 ` Ryan Mallon
2011-09-01 1:38 ` Mark Salter
2011-09-01 1:54 ` Ryan Mallon
2011-09-01 19:23 ` Mark Salter
2011-09-01 23:34 ` Ryan Mallon
2011-08-31 21:26 ` [PATCH 02/24] fixed generic page.h for non-zero PAGE_OFFSET Mark Salter
2011-08-31 21:26 ` Mark Salter
2011-08-31 21:26 ` [PATCH 03/24] add ELF machine define for TI C6X DSPs Mark Salter
2011-08-31 21:26 ` Mark Salter
2011-08-31 21:26 ` [PATCH 04/24] C6X: build infrastructure Mark Salter
2011-08-31 21:26 ` Mark Salter
2011-08-31 21:26 ` [PATCH 05/24] C6X: early boot code Mark Salter
2011-08-31 21:26 ` Mark Salter
2011-08-31 21:26 ` [PATCH 06/24] C6X: devicetree Mark Salter
2011-08-31 21:26 ` Mark Salter
2011-08-31 21:26 ` Mark Salter
2011-09-12 20:11 ` Grant Likely
2011-09-12 20:11 ` Grant Likely
2011-09-12 20:11 ` Grant Likely
2011-09-12 23:20 ` Mark Salter [this message]
2011-09-12 23:20 ` Mark Salter
2011-09-13 6:43 ` Arnd Bergmann
2011-09-13 12:39 ` Mark Salter
2011-09-13 12:39 ` Mark Salter
2011-09-13 15:33 ` Arnd Bergmann
2011-09-13 15:33 ` Arnd Bergmann
2011-09-13 17:54 ` Grant Likely
2011-09-13 20:11 ` Arnd Bergmann
2011-09-13 20:11 ` Arnd Bergmann
2011-09-13 22:26 ` Mark Salter
2011-09-13 22:26 ` Mark Salter
2011-08-31 21:26 ` [PATCH 07/24] C6X: memory management and DMA support Mark Salter
2011-08-31 21:26 ` Mark Salter
2011-08-31 21:26 ` [PATCH 08/24] C6X: process management Mark Salter
2011-08-31 21:26 ` Mark Salter
2011-08-31 21:26 ` [PATCH 09/24] C6X: signal management Mark Salter
2011-08-31 21:26 ` Mark Salter
2011-09-01 9:50 ` Matt Fleming
2011-09-01 9:50 ` Matt Fleming
2011-09-01 19:15 ` Mark Salter
2011-09-01 19:15 ` Mark Salter
2011-08-31 21:26 ` [PATCH 10/24] C6X: time management Mark Salter
2011-08-31 21:26 ` Mark Salter
2011-09-09 14:19 ` Thomas Gleixner
2011-09-09 14:19 ` Thomas Gleixner
2011-09-12 14:12 ` Mark Salter
2011-09-12 14:12 ` Mark Salter
2011-09-13 1:16 ` john stultz
2011-09-13 1:16 ` john stultz
2011-09-13 3:18 ` Mark Salter
2011-09-13 3:44 ` john stultz
2011-08-31 21:26 ` [PATCH 11/24] C6X: interrupt handling Mark Salter
2011-08-31 21:26 ` Mark Salter
2011-09-09 14:33 ` Thomas Gleixner
2011-09-09 14:33 ` Thomas Gleixner
2011-09-12 14:27 ` Mark Salter
2011-09-12 14:30 ` Thomas Gleixner
2011-09-12 20:01 ` Grant Likely
2011-08-31 21:26 ` [PATCH 12/24] C6X: syscalls Mark Salter
2011-08-31 21:26 ` Mark Salter
2011-08-31 21:26 ` [PATCH 13/24] C6X: traps Mark Salter
2011-08-31 21:26 ` Mark Salter
2011-08-31 21:26 ` [PATCH 14/24] C6X: clocks Mark Salter
2011-08-31 21:26 ` Mark Salter
2011-08-31 21:26 ` [PATCH 15/24] C6X: cache control Mark Salter
2011-08-31 21:26 ` Mark Salter
2011-08-31 21:26 ` [PATCH 16/24] C6X: loadable module support Mark Salter
2011-08-31 21:26 ` Mark Salter
2011-08-31 21:26 ` [PATCH 17/24] C6X: ptrace support Mark Salter
2011-08-31 21:26 ` Mark Salter
2011-08-31 21:26 ` [PATCH 18/24] C6X: headers Mark Salter
2011-08-31 21:26 ` Mark Salter
2011-08-31 21:26 ` [PATCH 19/24] C6X: library code Mark Salter
2011-08-31 21:26 ` Mark Salter
2011-08-31 21:26 ` [PATCH 20/24] C6X: general SoC support Mark Salter
2011-08-31 21:26 ` Mark Salter
2011-08-31 21:26 ` [PATCH 21/24] C6X: specific " Mark Salter
2011-08-31 21:26 ` Mark Salter
2011-08-31 21:26 ` [PATCH 22/24] C6X: EMIF - External Memory Interface Mark Salter
2011-08-31 21:26 ` Mark Salter
2011-08-31 21:26 ` [PATCH 23/24] C6X: Power and Sleep Controller Mark Salter
2011-08-31 21:26 ` Mark Salter
2011-08-31 21:34 ` [PATCH v2 00/24] C6X: New architecture patch set Mark Salter
2011-08-31 21:34 ` Mark Salter
-- strict thread matches above, loose matches on Subject: below --
2011-08-22 20:09 Mark Salter
2011-08-22 20:09 ` [PATCH 06/24] C6X: devicetree Mark Salter
2011-08-08 21:44 [PATCH 00/24] C6X: New architecture patch set Mark Salter
2011-08-08 21:44 ` [PATCH 06/24] C6X: devicetree Mark Salter
2011-08-09 16:14 ` Arnd Bergmann
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