From: Tomasz Figa <t.figa@samsung.com> To: linux-samsung-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, kyungmin.park@samsung.com, kgene.kim@samsung.com, m.szyprowski@samsung.com, t.figa@samsung.com, s.nawrocki@samsung.com, mturquette@linaro.org, thomas.abraham@linaro.org, a.hajda@samsung.com, l.majewski@samsung.com Subject: [PATCH 10/21] clk: samsung: exynos4: Add camera related clock definitions Date: Wed, 27 Mar 2013 12:02:47 +0100 [thread overview] Message-ID: <1364382178-25248-11-git-send-email-t.figa@samsung.com> (raw) In-Reply-To: <1364382178-25248-1-git-send-email-t.figa@samsung.com> From: Sylwester Nawrocki <s.nawrocki@samsung.com> This patch adds several gate and mux clocks related to camera and ISP blocks. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> --- .../devicetree/bindings/clock/exynos4-clock.txt | 20 +++++++++ drivers/clk/samsung/clk-exynos4.c | 50 ++++++++++++++-------- 2 files changed, 53 insertions(+), 17 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt index 51c572a..657b889 100644 --- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt @@ -198,6 +198,26 @@ Exynos4 SoC and this is specified where applicable. audss 348 mipi_hsi 349 Exynos4210 mdma2 350 Exynos4210 + pixelasyncm0 351 + pixelasyncm1 352 + fimc_lite0 353 Exynos4x12 + fimc_lite1 354 Exynos4x12 + ppmuispx 355 Exynos4x12 + ppmuispmx 356 Exynos4x12 + + [Mux Clocks] + + Clock ID SoC (if specific) + ----------------------------------------------- + + mout_fimc0 384 + mout_fimc1 385 + mout_fimc2 386 + mout_fimc3 387 + mout_cam0 388 + mout_cam1 389 + mout_csis0 390 + mout_csis1 391 Example 1: An example of a clock controller node is listed below. diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index 8c4cffb..728ffaf 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -87,6 +87,7 @@ #define E4210_MPLL_CON0 0x14108 #define SRC_CPU 0x14200 #define DIV_CPU0 0x14500 +#define E4X12_GATE_ISP0 0x18800 /* the exynos4 soc type */ enum exynos4_soc { @@ -136,7 +137,12 @@ enum exynos4_clks { uart4, i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c_hdmi, tsadc, spi0, spi1, spi2, i2s1, i2s2, pcm0, i2s0, pcm1, pcm2, pwm, slimbus, spdif, ac97, modemif, chipid, sysreg, hdmi_cec, mct, wdt, rtc, keyif, - audss, mipi_hsi, mdma2, + audss, mipi_hsi, mdma2, pixelasyncm0, pixelasyncm1, fimc_lite0, + fimc_lite1, ppmuispx, ppmuispmx, + + /* mux clocks */ + mout_fimc0 = 384, mout_fimc1, mout_fimc2, mout_fimc3, mout_cam0, + mout_cam1, mout_csis0, mout_csis1, nr_clks, }; @@ -314,14 +320,14 @@ struct samsung_mux_clock exynos4210_mux_clks[] __initdata = { MUX_A(mout_core, "mout_core", mout_core_p4210, SRC_CPU, 16, 1, "mout_core"), MUX_A(sclk_vpll, "sclk_vpll", sclk_vpll_p4210, SRC_TOP0, 8, 1, "sclk_vpll"), - MUX(none, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4), - MUX(none, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4), - MUX(none, "mout_fimc2", group1_p4210, SRC_CAM, 8, 4), - MUX(none, "mout_fimc3", group1_p4210, SRC_CAM, 12, 4), - MUX(none, "mout_cam0", group1_p4210, SRC_CAM, 16, 4), - MUX(none, "mout_cam1", group1_p4210, SRC_CAM, 20, 4), - MUX(none, "mout_csis0", group1_p4210, SRC_CAM, 24, 4), - MUX(none, "mout_csis1", group1_p4210, SRC_CAM, 28, 4), + MUX(mout_fimc0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4), + MUX(mout_fimc1, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4), + MUX(mout_fimc2, "mout_fimc2", group1_p4210, SRC_CAM, 8, 4), + MUX(mout_fimc3, "mout_fimc3", group1_p4210, SRC_CAM, 12, 4), + MUX(mout_cam0, "mout_cam0", group1_p4210, SRC_CAM, 16, 4), + MUX(mout_cam1, "mout_cam1", group1_p4210, SRC_CAM, 20, 4), + MUX(mout_csis0, "mout_csis0", group1_p4210, SRC_CAM, 24, 4), + MUX(mout_csis1, "mout_csis1", group1_p4210, SRC_CAM, 28, 4), MUX(none, "mout_mfc0", sclk_ampll_p4210, SRC_MFC, 0, 1), MUX(none, "mout_g3d0", sclk_ampll_p4210, SRC_G3D, 0, 1), MUX(none, "mout_fimd0", group1_p4210, SRC_LCD0, 0, 4), @@ -365,14 +371,14 @@ struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = { MUX_A(sclk_vpll, "sclk_vpll", mout_vpll_p, SRC_TOP0, 8, 1, "sclk_vpll"), MUX(mout_core, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1), - MUX(none, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4), - MUX(none, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4), - MUX(none, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4), - MUX(none, "mout_fimc3", group1_p4x12, SRC_CAM, 12, 4), - MUX(none, "mout_cam0", group1_p4x12, SRC_CAM, 16, 4), - MUX(none, "mout_cam1", group1_p4x12, SRC_CAM, 20, 4), - MUX(none, "mout_csis0", group1_p4x12, SRC_CAM, 24, 4), - MUX(none, "mout_csis1", group1_p4x12, SRC_CAM, 28, 4), + MUX(mout_fimc0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4), + MUX(mout_fimc1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4), + MUX(mout_fimc2, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4), + MUX(mout_fimc3, "mout_fimc3", group1_p4x12, SRC_CAM, 12, 4), + MUX(mout_cam0, "mout_cam0", group1_p4x12, SRC_CAM, 16, 4), + MUX(mout_cam1, "mout_cam1", group1_p4x12, SRC_CAM, 20, 4), + MUX(mout_csis0, "mout_csis0", group1_p4x12, SRC_CAM, 24, 4), + MUX(mout_csis1, "mout_csis1", group1_p4x12, SRC_CAM, 28, 4), MUX(none, "mout_mfc0", sclk_ampll_p4x12, SRC_MFC, 0, 1), MUX(none, "mout_g3d0", sclk_ampll_p4x12, SRC_G3D, 0, 1), MUX(none, "mout_fimd0", group1_p4x12, SRC_LCD0, 0, 4), @@ -587,6 +593,8 @@ struct samsung_gate_clock exynos4_gate_clks[] __initdata = { GATE_IP_CAM, 10, 0, 0, "sysmmu"), GATE_DA(smmu_jpeg, "exynos-sysmmu.3", "smmu_jpeg", "aclk160", GATE_IP_CAM, 11, 0, 0, "sysmmu"), + GATE(pixelasyncm0, "pxl_async0", "aclk160", GATE_IP_CAM, 17, 0, 0), + GATE(pixelasyncm1, "pxl_async1", "aclk160", GATE_IP_CAM, 18, 0, 0), GATE_DA(smmu_tv, "exynos-sysmmu.2", "smmu_tv", "aclk160", GATE_IP_TV, 4, 0, 0, "sysmmu"), GATE_DA(mfc, "s5p-mfc", "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0, "mfc"), @@ -721,6 +729,14 @@ struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = { E4X12_GATE_IP_MAUDIO, 2, 0, 0, "pcm"), GATE_DA(i2s0, "samsung-i2s.0", "i2s0", "aclk100", E4X12_GATE_IP_MAUDIO, 3, 0, 0, "iis"), + GATE(fimc_lite0, "lite0", "aclk200", E4X12_GATE_ISP0, 3, + CLK_IGNORE_UNUSED, 0), + GATE(fimc_lite1, "lite1", "aclk200", E4X12_GATE_ISP0, 4, + CLK_IGNORE_UNUSED, 0), + GATE(ppmuispmx, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20, + CLK_IGNORE_UNUSED, 0), + GATE(ppmuispx, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21, + CLK_IGNORE_UNUSED, 0), }; #ifdef CONFIG_OF -- 1.8.1.5
WARNING: multiple messages have this Message-ID (diff)
From: t.figa@samsung.com (Tomasz Figa) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 10/21] clk: samsung: exynos4: Add camera related clock definitions Date: Wed, 27 Mar 2013 12:02:47 +0100 [thread overview] Message-ID: <1364382178-25248-11-git-send-email-t.figa@samsung.com> (raw) In-Reply-To: <1364382178-25248-1-git-send-email-t.figa@samsung.com> From: Sylwester Nawrocki <s.nawrocki@samsung.com> This patch adds several gate and mux clocks related to camera and ISP blocks. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> --- .../devicetree/bindings/clock/exynos4-clock.txt | 20 +++++++++ drivers/clk/samsung/clk-exynos4.c | 50 ++++++++++++++-------- 2 files changed, 53 insertions(+), 17 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt index 51c572a..657b889 100644 --- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt @@ -198,6 +198,26 @@ Exynos4 SoC and this is specified where applicable. audss 348 mipi_hsi 349 Exynos4210 mdma2 350 Exynos4210 + pixelasyncm0 351 + pixelasyncm1 352 + fimc_lite0 353 Exynos4x12 + fimc_lite1 354 Exynos4x12 + ppmuispx 355 Exynos4x12 + ppmuispmx 356 Exynos4x12 + + [Mux Clocks] + + Clock ID SoC (if specific) + ----------------------------------------------- + + mout_fimc0 384 + mout_fimc1 385 + mout_fimc2 386 + mout_fimc3 387 + mout_cam0 388 + mout_cam1 389 + mout_csis0 390 + mout_csis1 391 Example 1: An example of a clock controller node is listed below. diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index 8c4cffb..728ffaf 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -87,6 +87,7 @@ #define E4210_MPLL_CON0 0x14108 #define SRC_CPU 0x14200 #define DIV_CPU0 0x14500 +#define E4X12_GATE_ISP0 0x18800 /* the exynos4 soc type */ enum exynos4_soc { @@ -136,7 +137,12 @@ enum exynos4_clks { uart4, i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c_hdmi, tsadc, spi0, spi1, spi2, i2s1, i2s2, pcm0, i2s0, pcm1, pcm2, pwm, slimbus, spdif, ac97, modemif, chipid, sysreg, hdmi_cec, mct, wdt, rtc, keyif, - audss, mipi_hsi, mdma2, + audss, mipi_hsi, mdma2, pixelasyncm0, pixelasyncm1, fimc_lite0, + fimc_lite1, ppmuispx, ppmuispmx, + + /* mux clocks */ + mout_fimc0 = 384, mout_fimc1, mout_fimc2, mout_fimc3, mout_cam0, + mout_cam1, mout_csis0, mout_csis1, nr_clks, }; @@ -314,14 +320,14 @@ struct samsung_mux_clock exynos4210_mux_clks[] __initdata = { MUX_A(mout_core, "mout_core", mout_core_p4210, SRC_CPU, 16, 1, "mout_core"), MUX_A(sclk_vpll, "sclk_vpll", sclk_vpll_p4210, SRC_TOP0, 8, 1, "sclk_vpll"), - MUX(none, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4), - MUX(none, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4), - MUX(none, "mout_fimc2", group1_p4210, SRC_CAM, 8, 4), - MUX(none, "mout_fimc3", group1_p4210, SRC_CAM, 12, 4), - MUX(none, "mout_cam0", group1_p4210, SRC_CAM, 16, 4), - MUX(none, "mout_cam1", group1_p4210, SRC_CAM, 20, 4), - MUX(none, "mout_csis0", group1_p4210, SRC_CAM, 24, 4), - MUX(none, "mout_csis1", group1_p4210, SRC_CAM, 28, 4), + MUX(mout_fimc0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4), + MUX(mout_fimc1, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4), + MUX(mout_fimc2, "mout_fimc2", group1_p4210, SRC_CAM, 8, 4), + MUX(mout_fimc3, "mout_fimc3", group1_p4210, SRC_CAM, 12, 4), + MUX(mout_cam0, "mout_cam0", group1_p4210, SRC_CAM, 16, 4), + MUX(mout_cam1, "mout_cam1", group1_p4210, SRC_CAM, 20, 4), + MUX(mout_csis0, "mout_csis0", group1_p4210, SRC_CAM, 24, 4), + MUX(mout_csis1, "mout_csis1", group1_p4210, SRC_CAM, 28, 4), MUX(none, "mout_mfc0", sclk_ampll_p4210, SRC_MFC, 0, 1), MUX(none, "mout_g3d0", sclk_ampll_p4210, SRC_G3D, 0, 1), MUX(none, "mout_fimd0", group1_p4210, SRC_LCD0, 0, 4), @@ -365,14 +371,14 @@ struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = { MUX_A(sclk_vpll, "sclk_vpll", mout_vpll_p, SRC_TOP0, 8, 1, "sclk_vpll"), MUX(mout_core, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1), - MUX(none, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4), - MUX(none, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4), - MUX(none, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4), - MUX(none, "mout_fimc3", group1_p4x12, SRC_CAM, 12, 4), - MUX(none, "mout_cam0", group1_p4x12, SRC_CAM, 16, 4), - MUX(none, "mout_cam1", group1_p4x12, SRC_CAM, 20, 4), - MUX(none, "mout_csis0", group1_p4x12, SRC_CAM, 24, 4), - MUX(none, "mout_csis1", group1_p4x12, SRC_CAM, 28, 4), + MUX(mout_fimc0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4), + MUX(mout_fimc1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4), + MUX(mout_fimc2, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4), + MUX(mout_fimc3, "mout_fimc3", group1_p4x12, SRC_CAM, 12, 4), + MUX(mout_cam0, "mout_cam0", group1_p4x12, SRC_CAM, 16, 4), + MUX(mout_cam1, "mout_cam1", group1_p4x12, SRC_CAM, 20, 4), + MUX(mout_csis0, "mout_csis0", group1_p4x12, SRC_CAM, 24, 4), + MUX(mout_csis1, "mout_csis1", group1_p4x12, SRC_CAM, 28, 4), MUX(none, "mout_mfc0", sclk_ampll_p4x12, SRC_MFC, 0, 1), MUX(none, "mout_g3d0", sclk_ampll_p4x12, SRC_G3D, 0, 1), MUX(none, "mout_fimd0", group1_p4x12, SRC_LCD0, 0, 4), @@ -587,6 +593,8 @@ struct samsung_gate_clock exynos4_gate_clks[] __initdata = { GATE_IP_CAM, 10, 0, 0, "sysmmu"), GATE_DA(smmu_jpeg, "exynos-sysmmu.3", "smmu_jpeg", "aclk160", GATE_IP_CAM, 11, 0, 0, "sysmmu"), + GATE(pixelasyncm0, "pxl_async0", "aclk160", GATE_IP_CAM, 17, 0, 0), + GATE(pixelasyncm1, "pxl_async1", "aclk160", GATE_IP_CAM, 18, 0, 0), GATE_DA(smmu_tv, "exynos-sysmmu.2", "smmu_tv", "aclk160", GATE_IP_TV, 4, 0, 0, "sysmmu"), GATE_DA(mfc, "s5p-mfc", "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0, "mfc"), @@ -721,6 +729,14 @@ struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = { E4X12_GATE_IP_MAUDIO, 2, 0, 0, "pcm"), GATE_DA(i2s0, "samsung-i2s.0", "i2s0", "aclk100", E4X12_GATE_IP_MAUDIO, 3, 0, 0, "iis"), + GATE(fimc_lite0, "lite0", "aclk200", E4X12_GATE_ISP0, 3, + CLK_IGNORE_UNUSED, 0), + GATE(fimc_lite1, "lite1", "aclk200", E4X12_GATE_ISP0, 4, + CLK_IGNORE_UNUSED, 0), + GATE(ppmuispmx, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20, + CLK_IGNORE_UNUSED, 0), + GATE(ppmuispx, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21, + CLK_IGNORE_UNUSED, 0), }; #ifdef CONFIG_OF -- 1.8.1.5
next prev parent reply other threads:[~2013-03-27 11:06 UTC|newest] Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top 2013-03-27 11:02 [PATCH 00/21] Various fixes and extensions to Exynos4 clock driver Tomasz Figa 2013-03-27 11:02 ` Tomasz Figa 2013-03-27 11:02 ` [PATCH 01/21] clk: samsung: exynos4: Correct sclk_mfc clock definition Tomasz Figa 2013-03-27 11:02 ` Tomasz Figa 2013-03-27 11:02 ` [PATCH 02/21] clk: samsung: exynos4: Use mout_mpll_user_* on Exynos4x12 Tomasz Figa 2013-03-27 11:02 ` Tomasz Figa 2013-03-27 11:02 ` [PATCH 03/21] clk: samsung: exynos4: Add missing mout_mipihsi clock Tomasz Figa 2013-03-27 11:02 ` Tomasz Figa 2013-03-27 11:02 ` [PATCH 04/21] clk: samsung: exynos4: Add missing sclk_audio0 clock Tomasz Figa 2013-03-27 11:02 ` Tomasz Figa 2013-03-27 11:02 ` [PATCH 05/21] clk: samsung: exynos4: Export sclk_pcm0 Tomasz Figa 2013-03-27 11:02 ` Tomasz Figa 2013-03-27 11:02 ` [PATCH 06/21] clk: samsung: exynos4: Move dac and mixer to Exynos4210-specific clocks Tomasz Figa 2013-03-27 11:02 ` Tomasz Figa 2013-03-27 11:02 ` [PATCH 07/21] clk: samsung: exynos4: Export clocks used by exynos cpufreq drivers Tomasz Figa 2013-03-27 11:02 ` Tomasz Figa 2013-03-27 11:02 ` [PATCH 08/21] clk: samsung: pll: Remove unimplemented ops Tomasz Figa 2013-03-27 11:02 ` Tomasz Figa 2013-03-27 11:02 ` [PATCH 09/21] clk: samsung: exynos4: Export mout_core clock of Exynos4210 Tomasz Figa 2013-03-27 11:02 ` Tomasz Figa 2013-03-27 11:02 ` Tomasz Figa [this message] 2013-03-27 11:02 ` [PATCH 10/21] clk: samsung: exynos4: Add camera related clock definitions Tomasz Figa 2013-03-27 11:02 ` [PATCH 11/21] clk: samsung: exynos4: Add G3D clocks Tomasz Figa 2013-03-27 11:02 ` Tomasz Figa 2013-03-27 11:02 ` [PATCH 12/21] clk: samsung: exynos4: Add missing CMU_TOP and ISP clocks Tomasz Figa 2013-03-27 11:02 ` Tomasz Figa 2013-03-27 11:02 ` [PATCH 13/21] clk: samsung: exynos4: Add missing mout_sata on Exynos4210 Tomasz Figa 2013-03-27 11:02 ` Tomasz Figa 2013-03-27 11:02 ` [PATCH 14/21] clk: samsung: exynos4: Define {E,V}PLL registers Tomasz Figa 2013-03-27 11:02 ` Tomasz Figa 2013-03-27 11:02 ` [PATCH 15/21] clk: samsung: exynos4: Use SRC_MASK_PERIL{0,1} definitions Tomasz Figa 2013-03-27 11:02 ` Tomasz Figa 2013-03-27 11:02 ` [PATCH 16/21] clk: samsung: exynos4: Remove SoC-specific registers from save list Tomasz Figa 2013-03-27 11:02 ` Tomasz Figa 2013-03-27 11:02 ` [PATCH 17/21] clk: samsung: exynos4: Add E4210 prefix to LCD1 clock registers Tomasz Figa 2013-03-27 11:02 ` Tomasz Figa 2013-03-27 11:02 ` [PATCH 18/21] clk: samsung: exynos4: Add E4210 prefix to GATE_IP_PERIR register Tomasz Figa 2013-03-27 11:02 ` Tomasz Figa 2013-03-27 11:02 ` [PATCH 19/21] clk: samsung: exynos4: Remove E4X12 prefix from SRC_DMC register Tomasz Figa 2013-03-27 11:02 ` Tomasz Figa 2013-03-27 11:02 ` [PATCH 20/21] clk: samsung: exynos4: Add missing registers to suspend save list Tomasz Figa 2013-03-27 11:02 ` Tomasz Figa 2013-03-27 11:02 ` [PATCH 21/21] clk: samsung: exynos4: Add support for SoC-specific register " Tomasz Figa 2013-03-27 11:02 ` Tomasz Figa 2013-03-30 10:03 ` [PATCH 00/21] Various fixes and extensions to Exynos4 clock driver Thomas Abraham 2013-03-30 10:03 ` Thomas Abraham 2013-03-30 11:30 ` Tomasz Figa 2013-03-30 11:30 ` Tomasz Figa 2013-04-02 8:30 ` Kukjin Kim 2013-04-02 8:30 ` Kukjin Kim 2013-04-03 22:01 ` Mike Turquette 2013-04-03 22:01 ` Mike Turquette 2013-04-04 0:36 ` Kukjin Kim 2013-04-04 0:36 ` Kukjin Kim
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=1364382178-25248-11-git-send-email-t.figa@samsung.com \ --to=t.figa@samsung.com \ --cc=a.hajda@samsung.com \ --cc=kgene.kim@samsung.com \ --cc=kyungmin.park@samsung.com \ --cc=l.majewski@samsung.com \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-samsung-soc@vger.kernel.org \ --cc=m.szyprowski@samsung.com \ --cc=mturquette@linaro.org \ --cc=s.nawrocki@samsung.com \ --cc=thomas.abraham@linaro.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.