From: Tomasz Figa <t.figa@samsung.com>
To: linux-arm-kernel@lists.infradead.org
Cc: linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org,
Kukjin Kim <kgene.kim@samsung.com>,
Mike Turquette <mturquette@linaro.org>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Mark Rutland <mark.rutland@arm.com>,
Pawel Moll <pawel.moll@arm.com>,
Rob Herring <rob.herring@calxeda.com>,
Stephen Warren <swarren@wwwdotorg.org>,
Thomas Abraham <thomas.abraham@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Tushar Behera <tushar.behera@linaro.org>,
Yadwinder Singh Brar <yadi.brar@samsung.com>,
Doug Anderson <dianders@chromium.org>,
Kumar Gala <galak@codeaurora.org>,
Tomasz Figa <t.figa@samsung.com>,
Kyungmin Park <kyungmin.park@samsung.com>
Subject: [PATCH 08/16] clk: samsung: exynos4: Rename exynos4_plls to exynos4x12_plls
Date: Tue, 20 Aug 2013 19:31:35 +0200 [thread overview]
Message-ID: <1377019903-14614-9-git-send-email-t.figa@samsung.com> (raw)
In-Reply-To: <1377019903-14614-1-git-send-email-t.figa@samsung.com>
This array defines PLLs specific to Exynos 4x12 SoCs and not for all
Exynos 4 SoCs, so the name should represent that.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
drivers/clk/samsung/clk-exynos4.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index f1b61fe..febdce2 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -988,7 +988,7 @@ static struct of_device_id ext_clk_match[] __initdata = {
{},
};
-static struct samsung_pll_clock exynos4_plls[nr_plls] __initdata = {
+static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = {
[apll] = PLL(pll_35xx, fout_apll, "fout_apll", "fin_pll",
APLL_LOCK, APLL_CON0, NULL),
[mpll] = PLL(pll_35xx, fout_mpll, "fout_mpll", "fin_pll",
@@ -1040,8 +1040,8 @@ static void __init exynos4_clk_init(struct device_node *np,
samsung_clk_add_lookup(epll, fout_epll);
samsung_clk_add_lookup(vpll, fout_vpll);
} else {
- samsung_clk_register_pll(exynos4_plls,
- ARRAY_SIZE(exynos4_plls), reg_base);
+ samsung_clk_register_pll(exynos4x12_plls,
+ ARRAY_SIZE(exynos4x12_plls), reg_base);
}
samsung_clk_register_fixed_rate(exynos4_fixed_rate_clks,
--
1.8.3.2
WARNING: multiple messages have this Message-ID (diff)
From: t.figa@samsung.com (Tomasz Figa)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 08/16] clk: samsung: exynos4: Rename exynos4_plls to exynos4x12_plls
Date: Tue, 20 Aug 2013 19:31:35 +0200 [thread overview]
Message-ID: <1377019903-14614-9-git-send-email-t.figa@samsung.com> (raw)
In-Reply-To: <1377019903-14614-1-git-send-email-t.figa@samsung.com>
This array defines PLLs specific to Exynos 4x12 SoCs and not for all
Exynos 4 SoCs, so the name should represent that.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
drivers/clk/samsung/clk-exynos4.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index f1b61fe..febdce2 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -988,7 +988,7 @@ static struct of_device_id ext_clk_match[] __initdata = {
{},
};
-static struct samsung_pll_clock exynos4_plls[nr_plls] __initdata = {
+static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = {
[apll] = PLL(pll_35xx, fout_apll, "fout_apll", "fin_pll",
APLL_LOCK, APLL_CON0, NULL),
[mpll] = PLL(pll_35xx, fout_mpll, "fout_mpll", "fin_pll",
@@ -1040,8 +1040,8 @@ static void __init exynos4_clk_init(struct device_node *np,
samsung_clk_add_lookup(epll, fout_epll);
samsung_clk_add_lookup(vpll, fout_vpll);
} else {
- samsung_clk_register_pll(exynos4_plls,
- ARRAY_SIZE(exynos4_plls), reg_base);
+ samsung_clk_register_pll(exynos4x12_plls,
+ ARRAY_SIZE(exynos4x12_plls), reg_base);
}
samsung_clk_register_fixed_rate(exynos4_fixed_rate_clks,
--
1.8.3.2
next prev parent reply other threads:[~2013-08-20 17:32 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-08-20 17:31 [PATCH 00/16] Exynos clock clean-up for 3.12 Tomasz Figa
2013-08-20 17:31 ` Tomasz Figa
2013-08-20 17:31 ` [PATCH 01/16] pwm: samsung: Update DT bindings documentation to cover clocks Tomasz Figa
2013-08-20 17:31 ` Tomasz Figa
2013-08-20 20:34 ` Stephen Warren
2013-08-20 20:34 ` Stephen Warren
2013-08-20 22:32 ` Tomasz Figa
2013-08-20 22:32 ` Tomasz Figa
2013-08-20 17:31 ` [PATCH 02/16] ARM: dts: exynos4: Specify PWM clocks in PWM node Tomasz Figa
2013-08-20 17:31 ` Tomasz Figa
2013-08-20 17:31 ` [PATCH 03/16] clocksource: samsung_pwm_timer: Get clock from device tree Tomasz Figa
2013-08-20 17:31 ` Tomasz Figa
2013-08-20 17:31 ` [PATCH 04/16] clk: samsung: exynos4: Use separate aliases for cpufreq related clocks Tomasz Figa
2013-08-20 17:31 ` Tomasz Figa
2013-08-20 17:31 ` [PATCH 05/16] clk: samsung: Modify _get_rate() helper to use __clk_lookup() Tomasz Figa
2013-08-20 17:31 ` Tomasz Figa
2013-08-20 17:31 ` [PATCH 06/16] clk: samsung: exynos4: Remove unused static clkdev aliases Tomasz Figa
2013-08-20 17:31 ` Tomasz Figa
2013-08-20 17:31 ` [PATCH 07/16] clk: samsung: exynos4: Remove checks for DT node Tomasz Figa
2013-08-20 17:31 ` Tomasz Figa
2013-08-20 17:31 ` Tomasz Figa [this message]
2013-08-20 17:31 ` [PATCH 08/16] clk: samsung: exynos4: Rename exynos4_plls to exynos4x12_plls Tomasz Figa
2013-08-20 17:31 ` [PATCH 09/16] clk: samsung: pll: Use new registration method for PLL45xx Tomasz Figa
2013-08-20 17:31 ` Tomasz Figa
2013-08-21 13:17 ` Yadwinder Singh Brar
2013-08-21 13:17 ` Yadwinder Singh Brar
2013-08-22 19:59 ` Stephen Warren
2013-08-22 19:59 ` Stephen Warren
2013-08-20 17:31 ` [PATCH 10/16] clk: samsung: pll: Add support for rate configuration of PLL45xx Tomasz Figa
2013-08-20 17:31 ` Tomasz Figa
2013-08-21 12:18 ` Yadwinder Singh Brar
2013-08-21 12:18 ` Yadwinder Singh Brar
2013-08-21 12:49 ` Tomasz Figa
2013-08-21 12:49 ` Tomasz Figa
2013-08-20 17:31 ` [PATCH 11/16] clk: samsung: pll: Use new registration method for PLL46xx Tomasz Figa
2013-08-20 17:31 ` Tomasz Figa
2013-08-20 17:31 ` [PATCH 12/16] clk: samsung: pll: Add support for rate configuration of PLL46xx Tomasz Figa
2013-08-20 17:31 ` Tomasz Figa
2013-08-21 12:32 ` Yadwinder Singh Brar
2013-08-21 12:32 ` Yadwinder Singh Brar
2013-08-21 12:44 ` Tomasz Figa
2013-08-21 12:44 ` Tomasz Figa
2013-08-21 13:12 ` Yadwinder Singh Brar
2013-08-21 13:12 ` Yadwinder Singh Brar
2013-08-20 17:31 ` [PATCH 13/16] clk: samsung: exynos4: Reorder registration of mout_vpllsrc Tomasz Figa
2013-08-20 17:31 ` Tomasz Figa
2013-08-20 17:31 ` [PATCH 14/16] clk: samsung: exynos4: Register PLL rate tables for Exynos4210 Tomasz Figa
2013-08-20 17:31 ` Tomasz Figa
2013-08-21 12:34 ` Yadwinder Singh Brar
2013-08-21 12:34 ` Yadwinder Singh Brar
2013-08-21 12:45 ` Tomasz Figa
2013-08-21 12:45 ` Tomasz Figa
2013-08-20 17:31 ` [PATCH 15/16] clk: samsung: exynos4: Register PLL rate tables for Exynos4x12 Tomasz Figa
2013-08-20 17:31 ` Tomasz Figa
2013-08-20 17:31 ` [PATCH 16/16] clk: samsung: exynos5250: Simplify registration of PLL rate tables Tomasz Figa
2013-08-20 17:31 ` Tomasz Figa
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