From: Addy Ke <addy.ke@rock-chips.com>
To: wsa@the-dreams.de, max.schwarz@online.de, heiko@sntech.de,
olof@lixom.net, dianders@chromium.org
Cc: linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, cf@rock-chips.com,
xjq@rock-chips.com, huangtao@rock-chips.com, zyw@rock-chips.com,
yzq@rock-chips.com, hj@rock-chips.com, kever.yang@rock-chips.com,
hl@rock-chips.com, caesar.wang@rock-chips.com,
zhengsq@rock-chips.com, Addy Ke <addy.ke@rock-chips.com>
Subject: [PATCH v2] i2c: rk3x: fix divisor calculation for SCL frequency
Date: Mon, 8 Sep 2014 11:38:25 +0800 [thread overview]
Message-ID: <1410147505-5930-1-git-send-email-addy.ke@rock-chips.com> (raw)
In-Reply-To: <1409884333-3544-1-git-send-email-addy.ke@rock-chips.com>
I2C_CLKDIV register descripted in the previous version of
RK3x chip manual is incorrect. Plus 1 is required.
The correct formula:
- T(SCL_HIGH) = T(PCLK) * (CLKDIVH + 1) * 8
- T(SCL_LOW) = T(PCLK) * (CLKDIVL + 1) * 8
- (SCL Divsor) = 8 * ((CLKDIVL + 1) + (CLKDIVH + 1))
- SCL = PCLK / (CLK Divsor)
It will be updated to the latest version of chip manual.
Signed-off-by: Addy Ke <addy.ke@rock-chips.com>
---
changes since v1:
- make it more cleaner, suggested by Doug Anderson
drivers/i2c/busses/i2c-rk3x.c | 11 +++++------
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/i2c/busses/i2c-rk3x.c b/drivers/i2c/busses/i2c-rk3x.c
index e637c32..93cfc83 100644
--- a/drivers/i2c/busses/i2c-rk3x.c
+++ b/drivers/i2c/busses/i2c-rk3x.c
@@ -433,12 +433,11 @@ static void rk3x_i2c_set_scl_rate(struct rk3x_i2c *i2c, unsigned long scl_rate)
unsigned long i2c_rate = clk_get_rate(i2c->clk);
unsigned int div;
- /* SCL rate = (clk rate) / (8 * DIV) */
- div = DIV_ROUND_UP(i2c_rate, scl_rate * 8);
-
- /* The lower and upper half of the CLKDIV reg describe the length of
- * SCL low & high periods. */
- div = DIV_ROUND_UP(div, 2);
+ /* set DIV = DIVH = DIVL
+ * SCL rate = (clk rate) / (8 * (DIVH + 1 + DIVL + 1))
+ * = (clk rate) / (16 * (DIV + 1))
+ */
+ div = DIV_ROUND_UP(i2c_rate, scl_rate * 16) - 1;
i2c_writel(i2c, (div << 16) | (div & 0xffff), REG_CLKDIV);
}
--
1.8.3.2
WARNING: multiple messages have this Message-ID (diff)
From: Addy Ke <addy.ke-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
To: wsa-z923LK4zBo2bacvFa/9K2g@public.gmane.org,
max.schwarz-BGeptl67XyCzQB+pC5nmwQ@public.gmane.org,
heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org,
olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org,
dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org
Cc: linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
cf-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
xjq-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
huangtao-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
zyw-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
yzq-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
hj-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
kever.yang-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
hl-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
caesar.wang-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
zhengsq-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
Addy Ke <addy.ke-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Subject: [PATCH v2] i2c: rk3x: fix divisor calculation for SCL frequency
Date: Mon, 8 Sep 2014 11:38:25 +0800 [thread overview]
Message-ID: <1410147505-5930-1-git-send-email-addy.ke@rock-chips.com> (raw)
In-Reply-To: <1409884333-3544-1-git-send-email-addy.ke-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
I2C_CLKDIV register descripted in the previous version of
RK3x chip manual is incorrect. Plus 1 is required.
The correct formula:
- T(SCL_HIGH) = T(PCLK) * (CLKDIVH + 1) * 8
- T(SCL_LOW) = T(PCLK) * (CLKDIVL + 1) * 8
- (SCL Divsor) = 8 * ((CLKDIVL + 1) + (CLKDIVH + 1))
- SCL = PCLK / (CLK Divsor)
It will be updated to the latest version of chip manual.
Signed-off-by: Addy Ke <addy.ke-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
changes since v1:
- make it more cleaner, suggested by Doug Anderson
drivers/i2c/busses/i2c-rk3x.c | 11 +++++------
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/i2c/busses/i2c-rk3x.c b/drivers/i2c/busses/i2c-rk3x.c
index e637c32..93cfc83 100644
--- a/drivers/i2c/busses/i2c-rk3x.c
+++ b/drivers/i2c/busses/i2c-rk3x.c
@@ -433,12 +433,11 @@ static void rk3x_i2c_set_scl_rate(struct rk3x_i2c *i2c, unsigned long scl_rate)
unsigned long i2c_rate = clk_get_rate(i2c->clk);
unsigned int div;
- /* SCL rate = (clk rate) / (8 * DIV) */
- div = DIV_ROUND_UP(i2c_rate, scl_rate * 8);
-
- /* The lower and upper half of the CLKDIV reg describe the length of
- * SCL low & high periods. */
- div = DIV_ROUND_UP(div, 2);
+ /* set DIV = DIVH = DIVL
+ * SCL rate = (clk rate) / (8 * (DIVH + 1 + DIVL + 1))
+ * = (clk rate) / (16 * (DIV + 1))
+ */
+ div = DIV_ROUND_UP(i2c_rate, scl_rate * 16) - 1;
i2c_writel(i2c, (div << 16) | (div & 0xffff), REG_CLKDIV);
}
--
1.8.3.2
WARNING: multiple messages have this Message-ID (diff)
From: addy.ke@rock-chips.com (Addy Ke)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2] i2c: rk3x: fix divisor calculation for SCL frequency
Date: Mon, 8 Sep 2014 11:38:25 +0800 [thread overview]
Message-ID: <1410147505-5930-1-git-send-email-addy.ke@rock-chips.com> (raw)
In-Reply-To: <1409884333-3544-1-git-send-email-addy.ke@rock-chips.com>
I2C_CLKDIV register descripted in the previous version of
RK3x chip manual is incorrect. Plus 1 is required.
The correct formula:
- T(SCL_HIGH) = T(PCLK) * (CLKDIVH + 1) * 8
- T(SCL_LOW) = T(PCLK) * (CLKDIVL + 1) * 8
- (SCL Divsor) = 8 * ((CLKDIVL + 1) + (CLKDIVH + 1))
- SCL = PCLK / (CLK Divsor)
It will be updated to the latest version of chip manual.
Signed-off-by: Addy Ke <addy.ke@rock-chips.com>
---
changes since v1:
- make it more cleaner, suggested by Doug Anderson
drivers/i2c/busses/i2c-rk3x.c | 11 +++++------
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/i2c/busses/i2c-rk3x.c b/drivers/i2c/busses/i2c-rk3x.c
index e637c32..93cfc83 100644
--- a/drivers/i2c/busses/i2c-rk3x.c
+++ b/drivers/i2c/busses/i2c-rk3x.c
@@ -433,12 +433,11 @@ static void rk3x_i2c_set_scl_rate(struct rk3x_i2c *i2c, unsigned long scl_rate)
unsigned long i2c_rate = clk_get_rate(i2c->clk);
unsigned int div;
- /* SCL rate = (clk rate) / (8 * DIV) */
- div = DIV_ROUND_UP(i2c_rate, scl_rate * 8);
-
- /* The lower and upper half of the CLKDIV reg describe the length of
- * SCL low & high periods. */
- div = DIV_ROUND_UP(div, 2);
+ /* set DIV = DIVH = DIVL
+ * SCL rate = (clk rate) / (8 * (DIVH + 1 + DIVL + 1))
+ * = (clk rate) / (16 * (DIV + 1))
+ */
+ div = DIV_ROUND_UP(i2c_rate, scl_rate * 16) - 1;
i2c_writel(i2c, (div << 16) | (div & 0xffff), REG_CLKDIV);
}
--
1.8.3.2
next prev parent reply other threads:[~2014-09-08 3:59 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-05 2:32 [PATCH] i2c: rk3x: fix divisor calculation for SCL frequency Addy Ke
2014-09-05 2:32 ` Addy Ke
2014-09-05 2:32 ` Addy Ke
2014-09-05 4:31 ` Doug Anderson
2014-09-05 4:31 ` Doug Anderson
2014-09-05 10:17 ` addy ke
2014-09-05 10:17 ` addy ke
2014-09-05 10:17 ` addy ke
2014-09-05 15:20 ` Doug Anderson
2014-09-05 15:20 ` Doug Anderson
2014-09-08 3:38 ` Addy Ke [this message]
2014-09-08 3:38 ` [PATCH v2] " Addy Ke
2014-09-08 3:38 ` Addy Ke
2014-09-08 4:15 ` Doug Anderson
2014-09-08 4:15 ` Doug Anderson
2014-09-20 12:19 ` Wolfram Sang
2014-09-20 12:19 ` Wolfram Sang
2014-09-20 12:19 ` Wolfram Sang
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