From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Intel-gfx@lists.freedesktop.org
Subject: [PATCH 1/8] drm/i915/skl: Add new displayable tiling formats
Date: Fri, 27 Feb 2015 11:15:17 +0000 [thread overview]
Message-ID: <1425035724-7123-2-git-send-email-tvrtko.ursulin@linux.intel.com> (raw)
In-Reply-To: <1425035724-7123-1-git-send-email-tvrtko.ursulin@linux.intel.com>
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Starting with SKL display engine can scan out Y, and newly introduced Yf
tiling formats so add the latter to the frame buffer modifier space.
v2: Definitions moved to drm_fourcc.h.
v3: Try to document the format better.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
---
include/uapi/drm/drm_fourcc.h | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 1a5a357..e6efac2 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -192,4 +192,19 @@
*/
#define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2)
+/*
+ * Intel Yf-tiling layout
+ *
+ * This is a tiled layout using 4Kb tiles in row-major layout.
+ * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
+ * are arranged in four groups (two wide, two high) with column-major layout.
+ * Each group therefore consits out of four 256 byte units, which are also laid
+ * out as 2x2 column-major.
+ * 256 byte units are made out of four 64 byte blocks of pixels, producing
+ * either a square block or a 2:1 unit.
+ * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width
+ * in pixel depends on the pixel depth.
+ */
+#define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)
+
#endif /* DRM_FOURCC_H */
--
2.3.0
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next prev parent reply other threads:[~2015-02-27 11:15 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-02-27 11:15 [PATCH v5 0/8] Skylake Y tiled scanout Tvrtko Ursulin
2015-02-27 11:15 ` Tvrtko Ursulin [this message]
2015-02-27 11:15 ` [PATCH 2/8] drm/i915/skl: Allow scanning out Y and Yf fbs Tvrtko Ursulin
2015-02-27 11:15 ` [PATCH 3/8] drm/i915/skl: Adjust intel_fb_align_height() for Yb/Yf tiling Tvrtko Ursulin
2015-02-27 11:15 ` [PATCH 4/8] drm/i915/skl: Teach pin_and_fence_fb_obj() about Y tiling constraints Tvrtko Ursulin
2015-02-27 11:15 ` [PATCH 5/8] drm/i915/skl: Adjust get_plane_config() to support Yb/Yf tiling Tvrtko Ursulin
2015-02-27 11:15 ` [PATCH 6/8] drm/i915/skl: Updated watermark programming Tvrtko Ursulin
2015-02-27 11:15 ` [PATCH 7/8] drm/i915/skl: Update watermarks for Y tiling Tvrtko Ursulin
2015-02-27 15:12 ` Tvrtko Ursulin
2015-02-27 11:15 ` [PATCH 8/8] drm/i915/skl: Allow Y (and Yf) frame buffer creation Tvrtko Ursulin
2015-02-27 15:27 ` [PATCH v5 0/8] Skylake Y tiled scanout Daniel Vetter
-- strict thread matches above, loose matches on Subject: below --
2015-02-25 16:47 [PATCH v4 " Tvrtko Ursulin
2015-02-25 16:47 ` [PATCH 1/8] drm/i915/skl: Add new displayable tiling formats Tvrtko Ursulin
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