Re: ongoing writecombine on ppc

From: Benjamin Herrenschmidt <benh@au1.ibm.com>
To: Dave Airlie <airlied@gmail.com>,
	Jerome Glisse <j.glisse@gmail.com>,
	Oded Gabbay <oded.gabbay@gmail.com>,
	dri-devel <dri-devel@lists.freedesktop.org>
Subject: Re: ongoing writecombine on ppc
Date: Fri, 02 Oct 2015 14:50:07 +1000	[thread overview]
Message-ID: <1443761407.2828.69.camel@au1.ibm.com> (raw)
In-Reply-To: <1443761238.2828.67.camel@au1.ibm.com>

On Fri, 2015-10-02 at 14:47 +1000, Benjamin Herrenschmidt wrote:
> On Fri, 2015-10-02 at 14:45 +1000, Benjamin Herrenschmidt wrote:
> > On Fri, 2015-10-02 at 14:42 +1000, Dave Airlie wrote:
> > > I don't think we resolved this the last time we talked about it,
> > > 
> > > but radeon writecombine maps fail hard on ppc, I think all the
> > > fixes
> > > either did something bad to AGP systems or weren't liked.
> > > 
> > > My patch attached just fixes radeon, which is where I'm still
> > > seeing
> > > the issue.
> > 
> > Yes, you MUST NOT set the flags of system memory to anything other
> > than
> > fully cachable on any cache coherent powerpc machine. This should
> > be
> > bolted into the DRM core imho.
> > 
> > _wc is only suitable for MMIO.
> 
> Note that I wouldn't be surprised if we weren't the only arch like
> that.
> 
> Playing with caching attributes of main memory smells from a system
> design and cache coherency protocol standpoint. x86 supports it but
> I wouldn't be surprised if some ARMs puke in interesting way as well.

Similarily I remember something in the TTM core at some point that
was trying to use the same caching attribtues for memory as the
original (MMIO) object when moving it.

That will blow up on POWER and possibly others. Here too, it's a
complete heresy for the core to assume that it can apply MMIO
attributes to system memory. I don't know if that still happens
though.

Cheers,
Ben.

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