From: Heiko Stuebner <heiko@sntech.de>
To: ulf.hansson@linaro.org
Cc: jh80.chung@samsung.com, linux-mmc@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, dianders@chromium.org,
amstan@chromium.org, Heiko Stuebner <heiko@sntech.de>
Subject: [PATCH v3 6/7] ARM: dts: rockchip: Add drive/sample clocks for rk3288 dw_mmc devices
Date: Mon, 12 Oct 2015 14:48:29 +0200 [thread overview]
Message-ID: <1444654110-32293-7-git-send-email-heiko@sntech.de> (raw)
In-Reply-To: <1444654110-32293-1-git-send-email-heiko@sntech.de>
From: Alexandru M Stan <amstan@chromium.org>
The drive/sample clocks can be phase shifted. The drive clock
could be used in a future patch to adjust hold times. The sample
clock is used for tuning.
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm/boot/dts/rk3288.dtsi | 20 ++++++++++++--------
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 27a397f6..37c5a02 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -225,8 +225,9 @@
sdmmc: dwmmc@ff0c0000 {
compatible = "rockchip,rk3288-dw-mshc";
clock-freq-min-max = <400000 150000000>;
- clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
- clock-names = "biu", "ciu";
+ clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
+ <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xff0c0000 0x4000>;
@@ -236,8 +237,9 @@
sdio0: dwmmc@ff0d0000 {
compatible = "rockchip,rk3288-dw-mshc";
clock-freq-min-max = <400000 150000000>;
- clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;
- clock-names = "biu", "ciu";
+ clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
+ <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xff0d0000 0x4000>;
@@ -247,8 +249,9 @@
sdio1: dwmmc@ff0e0000 {
compatible = "rockchip,rk3288-dw-mshc";
clock-freq-min-max = <400000 150000000>;
- clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;
- clock-names = "biu", "ciu";
+ clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
+ <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xff0e0000 0x4000>;
@@ -258,8 +261,9 @@
emmc: dwmmc@ff0f0000 {
compatible = "rockchip,rk3288-dw-mshc";
clock-freq-min-max = <400000 150000000>;
- clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
- clock-names = "biu", "ciu";
+ clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
+ <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xff0f0000 0x4000>;
--
2.6.1
WARNING: multiple messages have this Message-ID (diff)
From: heiko@sntech.de (Heiko Stuebner)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 6/7] ARM: dts: rockchip: Add drive/sample clocks for rk3288 dw_mmc devices
Date: Mon, 12 Oct 2015 14:48:29 +0200 [thread overview]
Message-ID: <1444654110-32293-7-git-send-email-heiko@sntech.de> (raw)
In-Reply-To: <1444654110-32293-1-git-send-email-heiko@sntech.de>
From: Alexandru M Stan <amstan@chromium.org>
The drive/sample clocks can be phase shifted. The drive clock
could be used in a future patch to adjust hold times. The sample
clock is used for tuning.
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm/boot/dts/rk3288.dtsi | 20 ++++++++++++--------
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 27a397f6..37c5a02 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -225,8 +225,9 @@
sdmmc: dwmmc at ff0c0000 {
compatible = "rockchip,rk3288-dw-mshc";
clock-freq-min-max = <400000 150000000>;
- clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
- clock-names = "biu", "ciu";
+ clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
+ <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xff0c0000 0x4000>;
@@ -236,8 +237,9 @@
sdio0: dwmmc at ff0d0000 {
compatible = "rockchip,rk3288-dw-mshc";
clock-freq-min-max = <400000 150000000>;
- clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;
- clock-names = "biu", "ciu";
+ clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
+ <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xff0d0000 0x4000>;
@@ -247,8 +249,9 @@
sdio1: dwmmc at ff0e0000 {
compatible = "rockchip,rk3288-dw-mshc";
clock-freq-min-max = <400000 150000000>;
- clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;
- clock-names = "biu", "ciu";
+ clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
+ <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xff0e0000 0x4000>;
@@ -258,8 +261,9 @@
emmc: dwmmc at ff0f0000 {
compatible = "rockchip,rk3288-dw-mshc";
clock-freq-min-max = <400000 150000000>;
- clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
- clock-names = "biu", "ciu";
+ clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
+ <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xff0f0000 0x4000>;
--
2.6.1
next prev parent reply other threads:[~2015-10-12 12:48 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-12 12:48 [PATCH v3 0/7] mmc: dw_mmc-rockchip: allow tuning using the clk-phase api Heiko Stuebner
2015-10-12 12:48 ` Heiko Stuebner
2015-10-12 12:48 ` [PATCH v3 1/7] mmc: core: move ocr-bit to voltage translation into separate function Heiko Stuebner
2015-10-12 12:48 ` Heiko Stuebner
2015-10-12 13:26 ` kbuild test robot
2015-10-12 13:26 ` kbuild test robot
2015-10-12 13:44 ` Heiko Stübner
2015-10-12 13:44 ` Heiko Stübner
[not found] ` <1444654110-32293-2-git-send-email-heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
2015-10-12 16:00 ` [PATCH v3.1 " Heiko Stübner
2015-10-12 16:00 ` Heiko Stübner
2015-10-12 12:48 ` [PATCH v3 2/7] mmc: core: Add mmc_regulator_set_vqmmc() Heiko Stuebner
2015-10-12 12:48 ` Heiko Stuebner
2015-10-12 12:48 ` [PATCH v3 3/7] mmc: dw_mmc: Use mmc_regulator_set_vqmmc in start_signal_voltage_switch Heiko Stuebner
2015-10-12 12:48 ` Heiko Stuebner
2015-10-12 12:48 ` [PATCH v3 4/7] mmc: dw_mmc-rockchip: dt-binding: Add tuning related things Heiko Stuebner
2015-10-12 12:48 ` Heiko Stuebner
2015-10-12 12:48 ` [PATCH v3 5/7] mmc: dw_mmc-rockchip: MMC tuning with the clock phase framework Heiko Stuebner
2015-10-12 12:48 ` Heiko Stuebner
2015-10-12 12:48 ` Heiko Stuebner [this message]
2015-10-12 12:48 ` [PATCH v3 6/7] ARM: dts: rockchip: Add drive/sample clocks for rk3288 dw_mmc devices Heiko Stuebner
2015-10-12 12:48 ` [PATCH v3 7/7] ARM: dts: rockchip: add tuning related settings to veyron devices Heiko Stuebner
2015-10-12 12:48 ` Heiko Stuebner
2015-10-16 8:25 ` [PATCH v3 0/7] mmc: dw_mmc-rockchip: allow tuning using the clk-phase api Ulf Hansson
2015-10-16 8:25 ` Ulf Hansson
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