From: Tomasz Figa <t.figa@samsung.com> To: Rahul Sharma <rahul.sharma@samsung.com> Cc: linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, mturquette@linaro.org, kgene.kim@samsung.com, thomas.ab@samsung.com, tomasz.figa@gmail.com, joshi@samsung.com, pankaj.dubey@samsung.com, yg1004.jang@samsung.com, arun.kk@samsung.com, r.sh.open@gmail.com Subject: Re: [PATCH 5/7] clk/samsung: add support for pll2550xx Date: Thu, 19 Dec 2013 13:01:18 +0100 [thread overview] Message-ID: <1450803.Oy1I8miDAj@amdc1227> (raw) In-Reply-To: <1386345391-23482-6-git-send-email-rahul.sharma@samsung.com> Hi Pankaj, Rahul, Arun, On Friday 06 of December 2013 21:26:29 Rahul Sharma wrote: > From: Pankaj Dubey <pankaj.dubey@samsung.com> > > exynos5260 use pll2520xx and it has different bitfields > for P,M,S values as compared to pll2550xx. Support for > pll2520xx is added here. > > Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> > Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> > Signed-off-by: Arun Kumar K <arun.kk@samsung.com> > --- > drivers/clk/samsung/clk-pll.c | 107 +++++++++++++++++++++++++++++++++++++++++ > drivers/clk/samsung/clk-pll.h | 1 + > 2 files changed, 108 insertions(+) > > diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c > index e8e8953..237a889 100644 > --- a/drivers/clk/samsung/clk-pll.c > +++ b/drivers/clk/samsung/clk-pll.c > @@ -710,6 +710,107 @@ struct clk * __init samsung_clk_register_pll2550x(const char *name, > return clk; > } > > +/* > + * PLL2550xx Clock Type > + */ > + > +/* Maximum lock time can be 270 * PDIV cycles */ > +#define PLL2550XX_LOCK_FACTOR (270) > + > +#define PLL2550XX_MDIV_MASK (0x3FF) > +#define PLL2550XX_PDIV_MASK (0x3F) > +#define PLL2550XX_SDIV_MASK (0x7) > +#define PLL2550XX_LOCK_STAT_MASK (0x1) > +#define PLL2550XX_MDIV_SHIFT (9) > +#define PLL2550XX_PDIV_SHIFT (3) > +#define PLL2550XX_SDIV_SHIFT (0) > +#define PLL2550XX_LOCK_STAT_SHIFT (21) > + > +static unsigned long samsung_pll2550xx_recalc_rate(struct clk_hw *hw, > + unsigned long parent_rate) > +{ > + struct samsung_clk_pll *pll = to_clk_pll(hw); > + u32 mdiv, pdiv, sdiv, pll_con; > + u64 fvco = parent_rate; > + > + pll_con = __raw_readl(pll->con_reg); > + mdiv = (pll_con >> PLL2550XX_MDIV_SHIFT) & PLL2550XX_MDIV_MASK; > + pdiv = (pll_con >> PLL2550XX_PDIV_SHIFT) & PLL2550XX_PDIV_MASK; > + sdiv = (pll_con >> PLL2550XX_SDIV_SHIFT) & PLL2550XX_SDIV_MASK; > + > + fvco *= mdiv; > + do_div(fvco, (pdiv << sdiv)); > + > + return (unsigned long)fvco; > +} > + > +static inline bool samsung_pll2550xx_mp_change(u32 mdiv, u32 pdiv, u32 pll_con) > +{ > + if ((mdiv != ((pll_con >> PLL2550XX_MDIV_SHIFT) & > + PLL2550XX_MDIV_MASK)) || > + (pdiv != ((pll_con >> PLL2550XX_PDIV_SHIFT) & > + PLL2550XX_PDIV_MASK))) > + return 1; > + else > + return 0; This doesn't look too good. Can you make this consistent with implementations of this helper for other PLLs, such as samsung_pll35xx_mp_change()? > +} > + > +static int samsung_pll2550xx_set_rate(struct clk_hw *hw, unsigned long drate, > + unsigned long prate) > +{ > + struct samsung_clk_pll *pll = to_clk_pll(hw); > + const struct samsung_pll_rate_table *rate; > + u32 tmp; > + > + /* Get required rate settings from table */ > + rate = samsung_get_pll_settings(pll, drate); > + if (!rate) { > + pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, > + drate, __clk_get_name(hw->clk)); > + return -EINVAL; > + } > + > + tmp = __raw_readl(pll->con_reg); > + > + if (!(samsung_pll2550xx_mp_change(rate->mdiv, rate->pdiv, tmp))) { > + /* If only s change, change just s value only*/ > + tmp &= ~(PLL2550XX_SDIV_MASK << PLL2550XX_SDIV_SHIFT); > + tmp |= rate->sdiv << PLL2550XX_SDIV_SHIFT; > + __raw_writel(tmp, pll->con_reg); > + } else { Please make coding style of this function consistent with implementations of this operation for other PLLs, such as samsung_pll35xx_set_rate(). Otherwise the patch looks fine. Best regards, Tomasz
WARNING: multiple messages have this Message-ID (diff)
From: t.figa@samsung.com (Tomasz Figa) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 5/7] clk/samsung: add support for pll2550xx Date: Thu, 19 Dec 2013 13:01:18 +0100 [thread overview] Message-ID: <1450803.Oy1I8miDAj@amdc1227> (raw) In-Reply-To: <1386345391-23482-6-git-send-email-rahul.sharma@samsung.com> Hi Pankaj, Rahul, Arun, On Friday 06 of December 2013 21:26:29 Rahul Sharma wrote: > From: Pankaj Dubey <pankaj.dubey@samsung.com> > > exynos5260 use pll2520xx and it has different bitfields > for P,M,S values as compared to pll2550xx. Support for > pll2520xx is added here. > > Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> > Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> > Signed-off-by: Arun Kumar K <arun.kk@samsung.com> > --- > drivers/clk/samsung/clk-pll.c | 107 +++++++++++++++++++++++++++++++++++++++++ > drivers/clk/samsung/clk-pll.h | 1 + > 2 files changed, 108 insertions(+) > > diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c > index e8e8953..237a889 100644 > --- a/drivers/clk/samsung/clk-pll.c > +++ b/drivers/clk/samsung/clk-pll.c > @@ -710,6 +710,107 @@ struct clk * __init samsung_clk_register_pll2550x(const char *name, > return clk; > } > > +/* > + * PLL2550xx Clock Type > + */ > + > +/* Maximum lock time can be 270 * PDIV cycles */ > +#define PLL2550XX_LOCK_FACTOR (270) > + > +#define PLL2550XX_MDIV_MASK (0x3FF) > +#define PLL2550XX_PDIV_MASK (0x3F) > +#define PLL2550XX_SDIV_MASK (0x7) > +#define PLL2550XX_LOCK_STAT_MASK (0x1) > +#define PLL2550XX_MDIV_SHIFT (9) > +#define PLL2550XX_PDIV_SHIFT (3) > +#define PLL2550XX_SDIV_SHIFT (0) > +#define PLL2550XX_LOCK_STAT_SHIFT (21) > + > +static unsigned long samsung_pll2550xx_recalc_rate(struct clk_hw *hw, > + unsigned long parent_rate) > +{ > + struct samsung_clk_pll *pll = to_clk_pll(hw); > + u32 mdiv, pdiv, sdiv, pll_con; > + u64 fvco = parent_rate; > + > + pll_con = __raw_readl(pll->con_reg); > + mdiv = (pll_con >> PLL2550XX_MDIV_SHIFT) & PLL2550XX_MDIV_MASK; > + pdiv = (pll_con >> PLL2550XX_PDIV_SHIFT) & PLL2550XX_PDIV_MASK; > + sdiv = (pll_con >> PLL2550XX_SDIV_SHIFT) & PLL2550XX_SDIV_MASK; > + > + fvco *= mdiv; > + do_div(fvco, (pdiv << sdiv)); > + > + return (unsigned long)fvco; > +} > + > +static inline bool samsung_pll2550xx_mp_change(u32 mdiv, u32 pdiv, u32 pll_con) > +{ > + if ((mdiv != ((pll_con >> PLL2550XX_MDIV_SHIFT) & > + PLL2550XX_MDIV_MASK)) || > + (pdiv != ((pll_con >> PLL2550XX_PDIV_SHIFT) & > + PLL2550XX_PDIV_MASK))) > + return 1; > + else > + return 0; This doesn't look too good. Can you make this consistent with implementations of this helper for other PLLs, such as samsung_pll35xx_mp_change()? > +} > + > +static int samsung_pll2550xx_set_rate(struct clk_hw *hw, unsigned long drate, > + unsigned long prate) > +{ > + struct samsung_clk_pll *pll = to_clk_pll(hw); > + const struct samsung_pll_rate_table *rate; > + u32 tmp; > + > + /* Get required rate settings from table */ > + rate = samsung_get_pll_settings(pll, drate); > + if (!rate) { > + pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, > + drate, __clk_get_name(hw->clk)); > + return -EINVAL; > + } > + > + tmp = __raw_readl(pll->con_reg); > + > + if (!(samsung_pll2550xx_mp_change(rate->mdiv, rate->pdiv, tmp))) { > + /* If only s change, change just s value only*/ > + tmp &= ~(PLL2550XX_SDIV_MASK << PLL2550XX_SDIV_SHIFT); > + tmp |= rate->sdiv << PLL2550XX_SDIV_SHIFT; > + __raw_writel(tmp, pll->con_reg); > + } else { Please make coding style of this function consistent with implementations of this operation for other PLLs, such as samsung_pll35xx_set_rate(). Otherwise the patch looks fine. Best regards, Tomasz
next prev parent reply other threads:[~2013-12-19 12:01 UTC|newest] Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top 2013-12-06 15:56 [PATCH 0/7] exynos: add basic support for exynos5260 SoC Rahul Sharma 2013-12-06 15:56 ` Rahul Sharma 2013-12-06 15:56 ` [PATCH 1/7] ARM: EXYNOS: initial board " Rahul Sharma 2013-12-06 15:56 ` Rahul Sharma 2013-12-09 6:23 ` Sachin Kamat 2013-12-09 6:23 ` Sachin Kamat 2013-12-09 6:33 ` Rahul Sharma 2013-12-09 6:33 ` Rahul Sharma [not found] ` <CAK9yfHzX1+Rp3DCZiJSjE7VO6+TaDW7iqUZVpgRNkjVJofWauA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2013-12-23 4:39 ` Rahul Sharma 2013-12-23 4:39 ` Rahul Sharma 2013-12-10 15:57 ` Tomasz Figa 2013-12-10 15:57 ` Tomasz Figa 2014-01-03 9:24 ` Rahul Sharma 2014-01-03 9:24 ` Rahul Sharma 2013-12-06 15:56 ` [PATCH 2/7] pinctrl: exynos: add exynos5260 SoC specific data Rahul Sharma 2013-12-06 15:56 ` Rahul Sharma 2013-12-09 4:51 ` Sachin Kamat 2013-12-09 4:51 ` Sachin Kamat 2013-12-09 6:36 ` Rahul Sharma 2013-12-09 6:36 ` Rahul Sharma 2014-01-03 9:25 ` Rahul Sharma 2014-01-03 9:25 ` Rahul Sharma 2013-12-10 16:04 ` Tomasz Figa 2013-12-10 16:04 ` Tomasz Figa 2014-01-03 9:26 ` Rahul Sharma 2014-01-03 9:26 ` Rahul Sharma [not found] ` <1386345391-23482-1-git-send-email-rahul.sharma-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> 2013-12-06 15:56 ` [PATCH 3/7] ARM: dts: add dts files for exynos5260 SoC Rahul Sharma 2013-12-06 15:56 ` Rahul Sharma 2013-12-10 17:10 ` Tomasz Figa 2013-12-10 17:10 ` Tomasz Figa 2014-01-06 9:40 ` Rahul Sharma 2014-01-06 9:40 ` Rahul Sharma 2013-12-06 15:56 ` [PATCH 7/7] clk/exynos5260: add clock file for exynos5260 Rahul Sharma 2013-12-06 15:56 ` [PATCH 4/7] clk/samsung: add support for multuple clock providers Rahul Sharma 2013-12-06 15:56 ` Rahul Sharma 2013-12-11 11:15 ` Tomasz Figa 2013-12-11 11:15 ` Tomasz Figa 2014-01-06 11:35 ` Rahul Sharma 2014-01-06 11:35 ` Rahul Sharma 2013-12-06 15:56 ` [PATCH 5/7] clk/samsung: add support for pll2550xx Rahul Sharma 2013-12-06 15:56 ` Rahul Sharma 2013-12-09 8:06 ` Sachin Kamat 2013-12-09 8:06 ` Sachin Kamat 2013-12-19 12:01 ` Tomasz Figa [this message] 2013-12-19 12:01 ` Tomasz Figa 2014-01-06 11:36 ` Rahul Sharma 2014-01-06 11:36 ` Rahul Sharma 2013-12-06 15:56 ` [PATCH 6/7] clk/samsung: add support for pll2650xx Rahul Sharma 2013-12-06 15:56 ` Rahul Sharma 2013-12-09 8:09 ` Sachin Kamat 2013-12-09 8:09 ` Sachin Kamat 2013-12-19 11:45 ` Tomasz Figa 2013-12-19 11:45 ` Tomasz Figa 2014-01-06 11:44 ` Rahul Sharma 2014-01-06 11:44 ` Rahul Sharma 2014-01-08 0:37 ` Tomasz Figa 2014-01-08 0:37 ` Tomasz Figa
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=1450803.Oy1I8miDAj@amdc1227 \ --to=t.figa@samsung.com \ --cc=arun.kk@samsung.com \ --cc=devicetree@vger.kernel.org \ --cc=joshi@samsung.com \ --cc=kgene.kim@samsung.com \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-samsung-soc@vger.kernel.org \ --cc=mturquette@linaro.org \ --cc=pankaj.dubey@samsung.com \ --cc=r.sh.open@gmail.com \ --cc=rahul.sharma@samsung.com \ --cc=thomas.ab@samsung.com \ --cc=tomasz.figa@gmail.com \ --cc=yg1004.jang@samsung.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.