From: "Horia Geantă" <horia.geanta@nxp.com> To: Herbert Xu <herbert@gondor.apana.org.au> Cc: <linux-crypto@vger.kernel.org>, "David S. Miller" <davem@davemloft.net>, Arnd Bergmann <arnd@arndb.de>, <linux-arch@vger.kernel.org>, <linux-kernel@vger.kernel.org> Subject: [PATCH v3 1/8] asm-generic/io.h: allow barriers in io{read,write}{16,32}be Date: Thu, 19 May 2016 18:10:43 +0300 [thread overview] Message-ID: <1463670643-2527-1-git-send-email-horia.geanta@nxp.com> (raw) In-Reply-To: <1463670405-1059-1-git-send-email-horia.geanta@nxp.com> While reviewing the addition of io{read,write}64be accessors, Arnd -finds a potential problem: "If an architecture overrides readq/writeq to have barriers but does not override ioread64be/iowrite64be, this will lack the barriers and behave differently from the little-endian version. I think the only affected architecture is ARC, since ARM and ARM64 both override the big-endian accessors to have the correct barriers, and all others don't use barriers at all." -suggests a fix for the same problem in existing code (16/32-bit accessors); the fix leads "to a double-swap on architectures that don't override the io{read,write}{16,32}be accessors, but it will work correctly on all architectures without them having to override these accessors." Suggested-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Horia Geantă <horia.geanta@nxp.com> --- include/asm-generic/io.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h index eed3bbe88c8a..b79fb2c248a1 100644 --- a/include/asm-generic/io.h +++ b/include/asm-generic/io.h @@ -613,7 +613,7 @@ static inline void iowrite32(u32 value, volatile void __iomem *addr) #define ioread16be ioread16be static inline u16 ioread16be(const volatile void __iomem *addr) { - return __be16_to_cpu(__raw_readw(addr)); + return swab16(readw(addr)); } #endif @@ -621,7 +621,7 @@ static inline u16 ioread16be(const volatile void __iomem *addr) #define ioread32be ioread32be static inline u32 ioread32be(const volatile void __iomem *addr) { - return __be32_to_cpu(__raw_readl(addr)); + return swab32(readl(addr)); } #endif @@ -629,7 +629,7 @@ static inline u32 ioread32be(const volatile void __iomem *addr) #define iowrite16be iowrite16be static inline void iowrite16be(u16 value, void volatile __iomem *addr) { - __raw_writew(__cpu_to_be16(value), addr); + writew(swab16(value), addr); } #endif @@ -637,7 +637,7 @@ static inline void iowrite16be(u16 value, void volatile __iomem *addr) #define iowrite32be iowrite32be static inline void iowrite32be(u32 value, volatile void __iomem *addr) { - __raw_writel(__cpu_to_be32(value), addr); + writel(swab32(value), addr); } #endif -- 2.4.4
WARNING: multiple messages have this Message-ID (diff)
From: "Horia Geantă" <horia.geanta@nxp.com> To: Herbert Xu <herbert@gondor.apana.org.au> Cc: linux-crypto@vger.kernel.org, "David S. Miller" <davem@davemloft.net>, Arnd Bergmann <arnd@arndb.de>, linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/8] asm-generic/io.h: allow barriers in io{read,write}{16,32}be Date: Thu, 19 May 2016 18:10:43 +0300 [thread overview] Message-ID: <1463670643-2527-1-git-send-email-horia.geanta@nxp.com> (raw) In-Reply-To: <1463670405-1059-1-git-send-email-horia.geanta@nxp.com> While reviewing the addition of io{read,write}64be accessors, Arnd -finds a potential problem: "If an architecture overrides readq/writeq to have barriers but does not override ioread64be/iowrite64be, this will lack the barriers and behave differently from the little-endian version. I think the only affected architecture is ARC, since ARM and ARM64 both override the big-endian accessors to have the correct barriers, and all others don't use barriers at all." -suggests a fix for the same problem in existing code (16/32-bit accessors); the fix leads "to a double-swap on architectures that don't override the io{read,write}{16,32}be accessors, but it will work correctly on all architectures without them having to override these accessors." Suggested-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Horia Geantă <horia.geanta@nxp.com> --- include/asm-generic/io.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h index eed3bbe88c8a..b79fb2c248a1 100644 --- a/include/asm-generic/io.h +++ b/include/asm-generic/io.h @@ -613,7 +613,7 @@ static inline void iowrite32(u32 value, volatile void __iomem *addr) #define ioread16be ioread16be static inline u16 ioread16be(const volatile void __iomem *addr) { - return __be16_to_cpu(__raw_readw(addr)); + return swab16(readw(addr)); } #endif @@ -621,7 +621,7 @@ static inline u16 ioread16be(const volatile void __iomem *addr) #define ioread32be ioread32be static inline u32 ioread32be(const volatile void __iomem *addr) { - return __be32_to_cpu(__raw_readl(addr)); + return swab32(readl(addr)); } #endif @@ -629,7 +629,7 @@ static inline u32 ioread32be(const volatile void __iomem *addr) #define iowrite16be iowrite16be static inline void iowrite16be(u16 value, void volatile __iomem *addr) { - __raw_writew(__cpu_to_be16(value), addr); + writew(swab16(value), addr); } #endif @@ -637,7 +637,7 @@ static inline void iowrite16be(u16 value, void volatile __iomem *addr) #define iowrite32be iowrite32be static inline void iowrite32be(u32 value, volatile void __iomem *addr) { - __raw_writel(__cpu_to_be32(value), addr); + writel(swab32(value), addr); } #endif -- 2.4.4
next prev parent reply other threads:[~2016-05-19 15:10 UTC|newest] Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-05-19 15:06 [PATCH v3 0/8] crypto: caam - add support for LS1043A SoC Horia Geantă 2016-05-19 15:10 ` Horia Geantă [this message] 2016-05-19 15:10 ` [PATCH v3 1/8] asm-generic/io.h: allow barriers in io{read,write}{16,32}be Horia Geantă 2016-05-19 15:10 ` [PATCH v3 2/8] asm-generic/io.h: add io{read,write}64 accessors Horia Geantă 2016-05-19 15:10 ` Horia Geantă 2016-05-19 15:11 ` [PATCH v3 3/8] arm64: add io{read,write}64be accessors Horia Geantă 2016-05-19 15:11 ` Horia Geantă 2016-05-19 15:11 ` Horia Geantă 2016-05-19 15:11 ` [PATCH v3 4/8] powerpc: add io{read,write}64 accessors Horia Geantă 2016-05-19 15:11 ` [PATCH v3 5/8] crypto: caam - fix offset field in hw sg entries Horia Geantă 2016-05-19 15:11 ` [PATCH v3 6/8] crypto: caam - handle core endianness != caam endianness Horia Geantă 2016-05-19 15:11 ` [PATCH v3 7/8] crypto: caam - add ARCH_LAYERSCAPE to supported architectures Horia Geantă 2016-05-19 15:11 ` [PATCH v3 8/8] arm64: dts: ls1043a: add crypto node Horia Geantă 2016-06-07 10:48 ` Herbert Xu 2016-05-31 10:15 ` [PATCH v3 0/8] crypto: caam - add support for LS1043A SoC Herbert Xu
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=1463670643-2527-1-git-send-email-horia.geanta@nxp.com \ --to=horia.geanta@nxp.com \ --cc=arnd@arndb.de \ --cc=davem@davemloft.net \ --cc=herbert@gondor.apana.org.au \ --cc=linux-arch@vger.kernel.org \ --cc=linux-crypto@vger.kernel.org \ --cc=linux-kernel@vger.kernel.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.