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From: Andre Przywara <andre.przywara@arm.com>
To: Marc Zyngier <marc.zyngier@arm.com>,
	Christoffer Dall <christoffer.dall@linaro.org>
Cc: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 19/57] KVM: arm/arm64: vgic-new: Add IRQ sync/flush framework
Date: Thu, 19 May 2016 19:07:58 +0100	[thread overview]
Message-ID: <1463681316-23039-20-git-send-email-andre.przywara@arm.com> (raw)
In-Reply-To: <1463681316-23039-1-git-send-email-andre.przywara@arm.com>

From: Marc Zyngier <marc.zyngier@arm.com>

Implement the framework for syncing IRQs between our emulation and
the list registers, which represent the guest's view of IRQs.
This is done in kvm_vgic_flush_hwstate and kvm_vgic_sync_hwstate,
which gets called on guest entry and exit.
The code talking to the actual GICv2/v3 hardware is added in the
following patches.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Eric Auger <eric.auger@linaro.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Eric Auger <eric.auger@linaro.org>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
---
Changelog RFC..v1:
- split out vgic_clear_lr() from vgic_populate_lr()
- rename vgic_populate_lrs() to vgic_flush_lr_state()
- clean all LRs when the distributor is disabled
- use list_del() instead of list_del_init()
- add comments to explain the direction of sync/flush_hwstate
- remove unneeded BUG_ON(in_interrupt()

Changelog v2 .. v3:
- remove bogus v2 specific rebase leftovers

Changelog v3 .. v4:
- amend locks requirements

Changelog v4 .. v5:
- add nested spinlock annotation
- refine comment about multiple-source SGIs

 include/kvm/vgic/vgic.h  |   4 +
 virt/kvm/arm/vgic/vgic.c | 192 +++++++++++++++++++++++++++++++++++++++++++++++
 virt/kvm/arm/vgic/vgic.h |   2 +
 3 files changed, 198 insertions(+)

diff --git a/include/kvm/vgic/vgic.h b/include/kvm/vgic/vgic.h
index 7b6ca90..9506267 100644
--- a/include/kvm/vgic/vgic.h
+++ b/include/kvm/vgic/vgic.h
@@ -190,6 +190,10 @@ int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid,
 #define vgic_valid_spi(k, i)	(((i) >= VGIC_NR_PRIVATE_IRQS) && \
 			((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS))
 
+bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu *vcpu);
+void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
+void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
+
 /**
  * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW
  *
diff --git a/virt/kvm/arm/vgic/vgic.c b/virt/kvm/arm/vgic/vgic.c
index bce17de..2e048a4 100644
--- a/virt/kvm/arm/vgic/vgic.c
+++ b/virt/kvm/arm/vgic/vgic.c
@@ -307,3 +307,195 @@ int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid,
 {
 	return vgic_update_irq_pending(kvm, cpuid, intid, level, false);
 }
+
+/**
+ * vgic_prune_ap_list - Remove non-relevant interrupts from the list
+ *
+ * @vcpu: The VCPU pointer
+ *
+ * Go over the list of "interesting" interrupts, and prune those that we
+ * won't have to consider in the near future.
+ */
+static void vgic_prune_ap_list(struct kvm_vcpu *vcpu)
+{
+	struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
+	struct vgic_irq *irq, *tmp;
+
+retry:
+	spin_lock(&vgic_cpu->ap_list_lock);
+
+	list_for_each_entry_safe(irq, tmp, &vgic_cpu->ap_list_head, ap_list) {
+		struct kvm_vcpu *target_vcpu, *vcpuA, *vcpuB;
+
+		spin_lock(&irq->irq_lock);
+
+		BUG_ON(vcpu != irq->vcpu);
+
+		target_vcpu = vgic_target_oracle(irq);
+
+		if (!target_vcpu) {
+			/*
+			 * We don't need to process this interrupt any
+			 * further, move it off the list.
+			 */
+			list_del(&irq->ap_list);
+			irq->vcpu = NULL;
+			spin_unlock(&irq->irq_lock);
+			continue;
+		}
+
+		if (target_vcpu == vcpu) {
+			/* We're on the right CPU */
+			spin_unlock(&irq->irq_lock);
+			continue;
+		}
+
+		/* This interrupt looks like it has to be migrated. */
+
+		spin_unlock(&irq->irq_lock);
+		spin_unlock(&vgic_cpu->ap_list_lock);
+
+		/*
+		 * Ensure locking order by always locking the smallest
+		 * ID first.
+		 */
+		if (vcpu->vcpu_id < target_vcpu->vcpu_id) {
+			vcpuA = vcpu;
+			vcpuB = target_vcpu;
+		} else {
+			vcpuA = target_vcpu;
+			vcpuB = vcpu;
+		}
+
+		spin_lock(&vcpuA->arch.vgic_cpu.ap_list_lock);
+		spin_lock_nested(&vcpuB->arch.vgic_cpu.ap_list_lock,
+				 SINGLE_DEPTH_NESTING);
+		spin_lock(&irq->irq_lock);
+
+		/*
+		 * If the affinity has been preserved, move the
+		 * interrupt around. Otherwise, it means things have
+		 * changed while the interrupt was unlocked, and we
+		 * need to replay this.
+		 *
+		 * In all cases, we cannot trust the list not to have
+		 * changed, so we restart from the beginning.
+		 */
+		if (target_vcpu == vgic_target_oracle(irq)) {
+			struct vgic_cpu *new_cpu = &target_vcpu->arch.vgic_cpu;
+
+			list_del(&irq->ap_list);
+			irq->vcpu = target_vcpu;
+			list_add_tail(&irq->ap_list, &new_cpu->ap_list_head);
+		}
+
+		spin_unlock(&irq->irq_lock);
+		spin_unlock(&vcpuB->arch.vgic_cpu.ap_list_lock);
+		spin_unlock(&vcpuA->arch.vgic_cpu.ap_list_lock);
+		goto retry;
+	}
+
+	spin_unlock(&vgic_cpu->ap_list_lock);
+}
+
+static inline void vgic_process_maintenance_interrupt(struct kvm_vcpu *vcpu)
+{
+}
+
+static inline void vgic_fold_lr_state(struct kvm_vcpu *vcpu)
+{
+}
+
+/* Requires the irq_lock to be held. */
+static inline void vgic_populate_lr(struct kvm_vcpu *vcpu,
+				    struct vgic_irq *irq, int lr)
+{
+	DEBUG_SPINLOCK_BUG_ON(!spin_is_locked(&irq->irq_lock));
+}
+
+static inline void vgic_clear_lr(struct kvm_vcpu *vcpu, int lr)
+{
+}
+
+static inline void vgic_set_underflow(struct kvm_vcpu *vcpu)
+{
+}
+
+/* Requires the ap_list_lock to be held. */
+static int compute_ap_list_depth(struct kvm_vcpu *vcpu)
+{
+	struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
+	struct vgic_irq *irq;
+	int count = 0;
+
+	DEBUG_SPINLOCK_BUG_ON(!spin_is_locked(&vgic_cpu->ap_list_lock));
+
+	list_for_each_entry(irq, &vgic_cpu->ap_list_head, ap_list) {
+		spin_lock(&irq->irq_lock);
+		/* GICv2 SGIs can count for more than one... */
+		if (vgic_irq_is_sgi(irq->intid) && irq->source)
+			count += hweight8(irq->source);
+		else
+			count++;
+		spin_unlock(&irq->irq_lock);
+	}
+	return count;
+}
+
+/* Requires the VCPU's ap_list_lock to be held. */
+static void vgic_flush_lr_state(struct kvm_vcpu *vcpu)
+{
+	struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
+	struct vgic_irq *irq;
+	int count = 0;
+
+	DEBUG_SPINLOCK_BUG_ON(!spin_is_locked(&vgic_cpu->ap_list_lock));
+
+	if (compute_ap_list_depth(vcpu) > kvm_vgic_global_state.nr_lr) {
+		vgic_set_underflow(vcpu);
+		vgic_sort_ap_list(vcpu);
+	}
+
+	list_for_each_entry(irq, &vgic_cpu->ap_list_head, ap_list) {
+		spin_lock(&irq->irq_lock);
+
+		if (unlikely(vgic_target_oracle(irq) != vcpu))
+			goto next;
+
+		/*
+		 * On a VGICv2 we can have SGIs with multiple sources, so
+		 * we loop here to hopefully get all of them in at once.
+		 */
+		do {
+			vgic_populate_lr(vcpu, irq, count++);
+		} while (irq->source && count < kvm_vgic_global_state.nr_lr);
+
+next:
+		spin_unlock(&irq->irq_lock);
+
+		if (count == kvm_vgic_global_state.nr_lr)
+			break;
+	}
+
+	vcpu->arch.vgic_cpu.used_lrs = count;
+
+	/* Nuke remaining LRs */
+	for ( ; count < kvm_vgic_global_state.nr_lr; count++)
+		vgic_clear_lr(vcpu, count);
+}
+
+/* Sync back the hardware VGIC state into our emulation after a guest's run. */
+void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
+{
+	vgic_process_maintenance_interrupt(vcpu);
+	vgic_fold_lr_state(vcpu);
+	vgic_prune_ap_list(vcpu);
+}
+
+/* Flush our emulation state into the GIC hardware before entering the guest. */
+void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
+{
+	spin_lock(&vcpu->arch.vgic_cpu.ap_list_lock);
+	vgic_flush_lr_state(vcpu);
+	spin_unlock(&vcpu->arch.vgic_cpu.ap_list_lock);
+}
diff --git a/virt/kvm/arm/vgic/vgic.h b/virt/kvm/arm/vgic/vgic.h
index c625767..29b96b9 100644
--- a/virt/kvm/arm/vgic/vgic.h
+++ b/virt/kvm/arm/vgic/vgic.h
@@ -16,6 +16,8 @@
 #ifndef __KVM_ARM_VGIC_NEW_H__
 #define __KVM_ARM_VGIC_NEW_H__
 
+#define vgic_irq_is_sgi(intid) ((intid) < VGIC_NR_SGIS)
+
 struct vgic_irq *vgic_get_irq(struct kvm *kvm, struct kvm_vcpu *vcpu,
 			      u32 intid);
 bool vgic_queue_irq_unlock(struct kvm *kvm, struct vgic_irq *irq);
-- 
2.8.2

WARNING: multiple messages have this Message-ID (diff)
From: andre.przywara@arm.com (Andre Przywara)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 19/57] KVM: arm/arm64: vgic-new: Add IRQ sync/flush framework
Date: Thu, 19 May 2016 19:07:58 +0100	[thread overview]
Message-ID: <1463681316-23039-20-git-send-email-andre.przywara@arm.com> (raw)
In-Reply-To: <1463681316-23039-1-git-send-email-andre.przywara@arm.com>

From: Marc Zyngier <marc.zyngier@arm.com>

Implement the framework for syncing IRQs between our emulation and
the list registers, which represent the guest's view of IRQs.
This is done in kvm_vgic_flush_hwstate and kvm_vgic_sync_hwstate,
which gets called on guest entry and exit.
The code talking to the actual GICv2/v3 hardware is added in the
following patches.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Eric Auger <eric.auger@linaro.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Eric Auger <eric.auger@linaro.org>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
---
Changelog RFC..v1:
- split out vgic_clear_lr() from vgic_populate_lr()
- rename vgic_populate_lrs() to vgic_flush_lr_state()
- clean all LRs when the distributor is disabled
- use list_del() instead of list_del_init()
- add comments to explain the direction of sync/flush_hwstate
- remove unneeded BUG_ON(in_interrupt()

Changelog v2 .. v3:
- remove bogus v2 specific rebase leftovers

Changelog v3 .. v4:
- amend locks requirements

Changelog v4 .. v5:
- add nested spinlock annotation
- refine comment about multiple-source SGIs

 include/kvm/vgic/vgic.h  |   4 +
 virt/kvm/arm/vgic/vgic.c | 192 +++++++++++++++++++++++++++++++++++++++++++++++
 virt/kvm/arm/vgic/vgic.h |   2 +
 3 files changed, 198 insertions(+)

diff --git a/include/kvm/vgic/vgic.h b/include/kvm/vgic/vgic.h
index 7b6ca90..9506267 100644
--- a/include/kvm/vgic/vgic.h
+++ b/include/kvm/vgic/vgic.h
@@ -190,6 +190,10 @@ int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid,
 #define vgic_valid_spi(k, i)	(((i) >= VGIC_NR_PRIVATE_IRQS) && \
 			((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS))
 
+bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu *vcpu);
+void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
+void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
+
 /**
  * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW
  *
diff --git a/virt/kvm/arm/vgic/vgic.c b/virt/kvm/arm/vgic/vgic.c
index bce17de..2e048a4 100644
--- a/virt/kvm/arm/vgic/vgic.c
+++ b/virt/kvm/arm/vgic/vgic.c
@@ -307,3 +307,195 @@ int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid,
 {
 	return vgic_update_irq_pending(kvm, cpuid, intid, level, false);
 }
+
+/**
+ * vgic_prune_ap_list - Remove non-relevant interrupts from the list
+ *
+ * @vcpu: The VCPU pointer
+ *
+ * Go over the list of "interesting" interrupts, and prune those that we
+ * won't have to consider in the near future.
+ */
+static void vgic_prune_ap_list(struct kvm_vcpu *vcpu)
+{
+	struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
+	struct vgic_irq *irq, *tmp;
+
+retry:
+	spin_lock(&vgic_cpu->ap_list_lock);
+
+	list_for_each_entry_safe(irq, tmp, &vgic_cpu->ap_list_head, ap_list) {
+		struct kvm_vcpu *target_vcpu, *vcpuA, *vcpuB;
+
+		spin_lock(&irq->irq_lock);
+
+		BUG_ON(vcpu != irq->vcpu);
+
+		target_vcpu = vgic_target_oracle(irq);
+
+		if (!target_vcpu) {
+			/*
+			 * We don't need to process this interrupt any
+			 * further, move it off the list.
+			 */
+			list_del(&irq->ap_list);
+			irq->vcpu = NULL;
+			spin_unlock(&irq->irq_lock);
+			continue;
+		}
+
+		if (target_vcpu == vcpu) {
+			/* We're on the right CPU */
+			spin_unlock(&irq->irq_lock);
+			continue;
+		}
+
+		/* This interrupt looks like it has to be migrated. */
+
+		spin_unlock(&irq->irq_lock);
+		spin_unlock(&vgic_cpu->ap_list_lock);
+
+		/*
+		 * Ensure locking order by always locking the smallest
+		 * ID first.
+		 */
+		if (vcpu->vcpu_id < target_vcpu->vcpu_id) {
+			vcpuA = vcpu;
+			vcpuB = target_vcpu;
+		} else {
+			vcpuA = target_vcpu;
+			vcpuB = vcpu;
+		}
+
+		spin_lock(&vcpuA->arch.vgic_cpu.ap_list_lock);
+		spin_lock_nested(&vcpuB->arch.vgic_cpu.ap_list_lock,
+				 SINGLE_DEPTH_NESTING);
+		spin_lock(&irq->irq_lock);
+
+		/*
+		 * If the affinity has been preserved, move the
+		 * interrupt around. Otherwise, it means things have
+		 * changed while the interrupt was unlocked, and we
+		 * need to replay this.
+		 *
+		 * In all cases, we cannot trust the list not to have
+		 * changed, so we restart from the beginning.
+		 */
+		if (target_vcpu == vgic_target_oracle(irq)) {
+			struct vgic_cpu *new_cpu = &target_vcpu->arch.vgic_cpu;
+
+			list_del(&irq->ap_list);
+			irq->vcpu = target_vcpu;
+			list_add_tail(&irq->ap_list, &new_cpu->ap_list_head);
+		}
+
+		spin_unlock(&irq->irq_lock);
+		spin_unlock(&vcpuB->arch.vgic_cpu.ap_list_lock);
+		spin_unlock(&vcpuA->arch.vgic_cpu.ap_list_lock);
+		goto retry;
+	}
+
+	spin_unlock(&vgic_cpu->ap_list_lock);
+}
+
+static inline void vgic_process_maintenance_interrupt(struct kvm_vcpu *vcpu)
+{
+}
+
+static inline void vgic_fold_lr_state(struct kvm_vcpu *vcpu)
+{
+}
+
+/* Requires the irq_lock to be held. */
+static inline void vgic_populate_lr(struct kvm_vcpu *vcpu,
+				    struct vgic_irq *irq, int lr)
+{
+	DEBUG_SPINLOCK_BUG_ON(!spin_is_locked(&irq->irq_lock));
+}
+
+static inline void vgic_clear_lr(struct kvm_vcpu *vcpu, int lr)
+{
+}
+
+static inline void vgic_set_underflow(struct kvm_vcpu *vcpu)
+{
+}
+
+/* Requires the ap_list_lock to be held. */
+static int compute_ap_list_depth(struct kvm_vcpu *vcpu)
+{
+	struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
+	struct vgic_irq *irq;
+	int count = 0;
+
+	DEBUG_SPINLOCK_BUG_ON(!spin_is_locked(&vgic_cpu->ap_list_lock));
+
+	list_for_each_entry(irq, &vgic_cpu->ap_list_head, ap_list) {
+		spin_lock(&irq->irq_lock);
+		/* GICv2 SGIs can count for more than one... */
+		if (vgic_irq_is_sgi(irq->intid) && irq->source)
+			count += hweight8(irq->source);
+		else
+			count++;
+		spin_unlock(&irq->irq_lock);
+	}
+	return count;
+}
+
+/* Requires the VCPU's ap_list_lock to be held. */
+static void vgic_flush_lr_state(struct kvm_vcpu *vcpu)
+{
+	struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
+	struct vgic_irq *irq;
+	int count = 0;
+
+	DEBUG_SPINLOCK_BUG_ON(!spin_is_locked(&vgic_cpu->ap_list_lock));
+
+	if (compute_ap_list_depth(vcpu) > kvm_vgic_global_state.nr_lr) {
+		vgic_set_underflow(vcpu);
+		vgic_sort_ap_list(vcpu);
+	}
+
+	list_for_each_entry(irq, &vgic_cpu->ap_list_head, ap_list) {
+		spin_lock(&irq->irq_lock);
+
+		if (unlikely(vgic_target_oracle(irq) != vcpu))
+			goto next;
+
+		/*
+		 * On a VGICv2 we can have SGIs with multiple sources, so
+		 * we loop here to hopefully get all of them in at once.
+		 */
+		do {
+			vgic_populate_lr(vcpu, irq, count++);
+		} while (irq->source && count < kvm_vgic_global_state.nr_lr);
+
+next:
+		spin_unlock(&irq->irq_lock);
+
+		if (count == kvm_vgic_global_state.nr_lr)
+			break;
+	}
+
+	vcpu->arch.vgic_cpu.used_lrs = count;
+
+	/* Nuke remaining LRs */
+	for ( ; count < kvm_vgic_global_state.nr_lr; count++)
+		vgic_clear_lr(vcpu, count);
+}
+
+/* Sync back the hardware VGIC state into our emulation after a guest's run. */
+void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
+{
+	vgic_process_maintenance_interrupt(vcpu);
+	vgic_fold_lr_state(vcpu);
+	vgic_prune_ap_list(vcpu);
+}
+
+/* Flush our emulation state into the GIC hardware before entering the guest. */
+void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
+{
+	spin_lock(&vcpu->arch.vgic_cpu.ap_list_lock);
+	vgic_flush_lr_state(vcpu);
+	spin_unlock(&vcpu->arch.vgic_cpu.ap_list_lock);
+}
diff --git a/virt/kvm/arm/vgic/vgic.h b/virt/kvm/arm/vgic/vgic.h
index c625767..29b96b9 100644
--- a/virt/kvm/arm/vgic/vgic.h
+++ b/virt/kvm/arm/vgic/vgic.h
@@ -16,6 +16,8 @@
 #ifndef __KVM_ARM_VGIC_NEW_H__
 #define __KVM_ARM_VGIC_NEW_H__
 
+#define vgic_irq_is_sgi(intid) ((intid) < VGIC_NR_SGIS)
+
 struct vgic_irq *vgic_get_irq(struct kvm *kvm, struct kvm_vcpu *vcpu,
 			      u32 intid);
 bool vgic_queue_irq_unlock(struct kvm *kvm, struct vgic_irq *irq);
-- 
2.8.2

  parent reply	other threads:[~2016-05-19 18:07 UTC|newest]

Thread overview: 118+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-05-19 18:07 [PATCH v5 00/57] KVM: arm/arm64: Rework virtual GIC emulation Andre Przywara
2016-05-19 18:07 ` Andre Przywara
2016-05-19 18:07 ` [PATCH v5 01/57] KVM: arm/arm64: vgic: streamline vgic_update_irq_pending() interface Andre Przywara
2016-05-19 18:07   ` Andre Przywara
2016-05-19 18:07 ` [PATCH v5 02/57] KVM: arm/arm64: vgic: avoid map in kvm_vgic_inject_mapped_irq() Andre Przywara
2016-05-19 18:07   ` Andre Przywara
2016-05-19 18:07 ` [PATCH v5 03/57] KVM: arm/arm64: vgic: avoid map in kvm_vgic_map_is_active() Andre Przywara
2016-05-19 18:07   ` Andre Przywara
2016-05-19 18:07 ` [PATCH v5 04/57] KVM: arm/arm64: vgic: avoid map in kvm_vgic_unmap_phys_irq() Andre Przywara
2016-05-19 18:07   ` Andre Przywara
2016-05-19 18:07 ` [PATCH v5 05/57] KVM: arm/arm64: Remove the IRQ field from struct irq_phys_map Andre Przywara
2016-05-19 18:07   ` Andre Przywara
2016-05-19 18:07 ` [PATCH v5 06/57] KVM: arm/arm64: arch_timer: Remove irq_phys_map Andre Przywara
2016-05-19 18:07   ` Andre Przywara
2016-05-19 18:07 ` [PATCH v5 07/57] KVM: arm/arm64: vgic: Remove irq_phys_map from interface Andre Przywara
2016-05-19 18:07   ` Andre Przywara
2016-05-19 18:07 ` [PATCH v5 08/57] KVM: arm/arm64: Move timer IRQ map to latest possible time Andre Przywara
2016-05-19 18:07   ` Andre Przywara
2016-05-19 18:07 ` [PATCH v5 09/57] KVM: arm/arm64: Get rid of vgic_cpu->nr_lr Andre Przywara
2016-05-19 18:07   ` Andre Przywara
2016-05-19 18:07 ` [PATCH v5 10/57] KVM: arm/arm64: Fix MMIO emulation data handling Andre Przywara
2016-05-19 18:07   ` Andre Przywara
2016-05-19 18:07 ` [PATCH v5 11/57] KVM: arm/arm64: Export mmio_read/write_bus Andre Przywara
2016-05-19 18:07   ` Andre Przywara
2016-05-19 18:07 ` [PATCH v5 12/57] KVM: arm/arm64: pmu: abstract access to number of SPIs Andre Przywara
2016-05-19 18:07   ` Andre Przywara
2016-05-19 18:07 ` [PATCH v5 13/57] KVM: arm/arm64: Provide functionality to pause and resume a guest Andre Przywara
2016-05-19 18:07   ` Andre Przywara
2016-05-19 18:07 ` [PATCH v5 14/57] KVM: arm/arm64: move GICv2 emulation defines into arm-gic-v3.h Andre Przywara
2016-05-19 18:07   ` Andre Przywara
2016-05-19 18:07 ` [PATCH v5 15/57] KVM: arm/arm64: vgic-new: Add data structure definitions Andre Przywara
2016-05-19 18:07   ` Andre Przywara
2016-05-19 18:07 ` [PATCH v5 16/57] KVM: arm/arm64: vgic-new: Add acccessor to new struct vgic_irq instance Andre Przywara
2016-05-19 18:07   ` Andre Przywara
2016-05-19 18:07 ` [PATCH v5 17/57] KVM: arm/arm64: vgic-new: Implement virtual IRQ injection Andre Przywara
2016-05-19 18:07   ` Andre Przywara
2016-05-19 18:07 ` [PATCH v5 18/57] KVM: arm/arm64: vgic-new: Add IRQ sorting Andre Przywara
2016-05-19 18:07   ` Andre Przywara
2016-05-19 18:07 ` Andre Przywara [this message]
2016-05-19 18:07   ` [PATCH v5 19/57] KVM: arm/arm64: vgic-new: Add IRQ sync/flush framework Andre Przywara
2016-05-19 18:07 ` [PATCH v5 20/57] KVM: arm/arm64: vgic-new: Add GICv2 world switch backend Andre Przywara
2016-05-19 18:07   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 21/57] KVM: arm/arm64: vgic-new: Add GICv3 " Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 22/57] KVM: arm/arm64: vgic-new: Implement kvm_vgic_vcpu_pending_irq Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 23/57] KVM: arm/arm64: vgic-new: Add MMIO handling framework Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 24/57] KVM: arm/arm64: vgic-new: Add GICv2 " Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 25/57] KVM: arm/arm64: vgic-new: Add CTLR, TYPER and IIDR handlers Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 26/57] KVM: arm/arm64: vgic-new: Add ENABLE registers handlers Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 27/57] KVM: arm/arm64: vgic-new: Add PENDING " Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 28/57] KVM: arm/arm64: vgic-new: Add ACTIVE " Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 29/57] KVM: arm/arm64: vgic-new: Add PRIORITY " Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 30/57] KVM: arm/arm64: vgic-new: Add CONFIG " Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 31/57] KVM: arm/arm64: vgic-new: Add TARGET " Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 32/57] KVM: arm/arm64: vgic-new: Add SGIR register handler Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 33/57] KVM: arm/arm64: vgic-new: Add SGIPENDR register handlers Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 34/57] KVM: arm/arm64: vgic-new: Add GICv3 MMIO handling framework Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 35/57] KVM: arm/arm64: vgic-new: Add GICv3 CTLR, IIDR, TYPER handlers Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 36/57] KVM: arm/arm64: vgic-new: Add GICv3 redistributor IIDR and TYPER handler Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 37/57] KVM: arm/arm64: vgic-new: Add GICv3 IDREGS register handler Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 38/57] KVM: arm/arm64: vgic-new: Add GICv3 IROUTER register handlers Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 39/57] KVM: arm/arm64: vgic-new: Add GICv3 SGI system register trap handler Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 40/57] KVM: arm/arm64: vgic-new: vgic_kvm_device: KVM device ops registration Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 41/57] KVM: arm/arm64: vgic-new: vgic_kvm_device: KVM_DEV_ARM_VGIC_GRP_NR_IRQS Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 42/57] KVM: arm/arm64: vgic-new: vgic_kvm_device: KVM_DEV_ARM_VGIC_GRP_CTRL Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 43/57] KVM: arm/arm64: vgic-new: vgic_kvm_device: implement kvm_vgic_addr Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 44/57] KVM: arm/arm64: vgic-new: vgic_kvm_device: KVM_DEV_ARM_VGIC_GRP_ADDR Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 45/57] KVM: arm/arm64: vgic-new: vgic_kvm_device: access to VGIC registers Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 46/57] KVM: arm/arm64: vgic-new: Export register access interface Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 47/57] KVM: arm/arm64: vgic-new: Add userland access to VGIC dist registers Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 48/57] KVM: arm/arm64: vgic-new: Add GICH_VMCR accessors Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 49/57] KVM: arm/arm64: vgic-new: Add userland GIC CPU interface access Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 50/57] KVM: arm/arm64: vgic-new: vgic_init: implement kvm_vgic_hyp_init Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 51/57] KVM: arm/arm64: vgic-new: vgic_init: implement vgic_create Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 52/57] KVM: arm/arm64: vgic-new: vgic_init: implement vgic_init Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 53/57] KVM: arm/arm64: vgic-new: vgic_init: implement map_resources Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 54/57] KVM: arm/arm64: vgic-new: Add vgic_v2/v3_enable Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 55/57] KVM: arm/arm64: vgic-new: Wire up irqfd injection Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 56/57] KVM: arm/arm64: vgic-new: implement mapped IRQ handling Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-19 18:08 ` [PATCH v5 57/57] KVM: arm/arm64: vgic-new: enable build Andre Przywara
2016-05-19 18:08   ` Andre Przywara
2016-05-20 15:04 ` [PATCH v5 00/57] KVM: arm/arm64: Rework virtual GIC emulation Christoffer Dall
2016-05-20 15:04   ` Christoffer Dall

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