From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: gregkh@linuxfoundation.org
Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH 13/13] coresight: add PM runtime calls to coresight_simple_func()
Date: Thu, 30 Jun 2016 10:22:19 -0600 [thread overview]
Message-ID: <1467303739-12543-14-git-send-email-mathieu.poirier@linaro.org> (raw)
In-Reply-To: <1467303739-12543-1-git-send-email-mathieu.poirier@linaro.org>
It is mandatory to enable a coresight block's power domain before
trying to access management registers. Otherwise the transaction
simply stalls, leading to a system hang.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
---
drivers/hwtracing/coresight/coresight-priv.h | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h
index ad975c58080d..decfd52b5dc3 100644
--- a/drivers/hwtracing/coresight/coresight-priv.h
+++ b/drivers/hwtracing/coresight/coresight-priv.h
@@ -16,6 +16,7 @@
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/coresight.h>
+#include <linux/pm_runtime.h>
/*
* Coresight management registers (0xf00-0xfcc)
@@ -42,8 +43,11 @@ static ssize_t name##_show(struct device *_dev, \
struct device_attribute *attr, char *buf) \
{ \
type *drvdata = dev_get_drvdata(_dev->parent); \
- return scnprintf(buf, PAGE_SIZE, "0x%x\n", \
- readl_relaxed(drvdata->base + offset)); \
+ u32 val; \
+ pm_runtime_get_sync(_dev->parent); \
+ val = readl_relaxed(drvdata->base + offset); \
+ pm_runtime_put_sync(_dev->parent); \
+ return scnprintf(buf, PAGE_SIZE, "0x%x\n", val); \
} \
static DEVICE_ATTR_RO(name)
--
2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: mathieu.poirier@linaro.org (Mathieu Poirier)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 13/13] coresight: add PM runtime calls to coresight_simple_func()
Date: Thu, 30 Jun 2016 10:22:19 -0600 [thread overview]
Message-ID: <1467303739-12543-14-git-send-email-mathieu.poirier@linaro.org> (raw)
In-Reply-To: <1467303739-12543-1-git-send-email-mathieu.poirier@linaro.org>
It is mandatory to enable a coresight block's power domain before
trying to access management registers. Otherwise the transaction
simply stalls, leading to a system hang.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
---
drivers/hwtracing/coresight/coresight-priv.h | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h
index ad975c58080d..decfd52b5dc3 100644
--- a/drivers/hwtracing/coresight/coresight-priv.h
+++ b/drivers/hwtracing/coresight/coresight-priv.h
@@ -16,6 +16,7 @@
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/coresight.h>
+#include <linux/pm_runtime.h>
/*
* Coresight management registers (0xf00-0xfcc)
@@ -42,8 +43,11 @@ static ssize_t name##_show(struct device *_dev, \
struct device_attribute *attr, char *buf) \
{ \
type *drvdata = dev_get_drvdata(_dev->parent); \
- return scnprintf(buf, PAGE_SIZE, "0x%x\n", \
- readl_relaxed(drvdata->base + offset)); \
+ u32 val; \
+ pm_runtime_get_sync(_dev->parent); \
+ val = readl_relaxed(drvdata->base + offset); \
+ pm_runtime_put_sync(_dev->parent); \
+ return scnprintf(buf, PAGE_SIZE, "0x%x\n", val); \
} \
static DEVICE_ATTR_RO(name)
--
2.7.4
next prev parent reply other threads:[~2016-06-30 16:29 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-30 16:22 [PATCH 00/13] coresight: next v4.7-rc5 Mathieu Poirier
2016-06-30 16:22 ` Mathieu Poirier
2016-06-30 16:22 ` [PATCH 01/13] coresight: access conn->child_name only if it's initialised Mathieu Poirier
2016-06-30 16:22 ` Mathieu Poirier
2016-06-30 16:22 ` [PATCH 02/13] coresight-stm: support mmapping channel regions with mmio_addr Mathieu Poirier
2016-06-30 16:22 ` Mathieu Poirier
2016-06-30 16:22 ` [PATCH 03/13] coresight: always use stashed trace id value in etm4_trace_id Mathieu Poirier
2016-06-30 16:22 ` Mathieu Poirier
2016-06-30 16:22 ` [PATCH 04/13] coresight: Remove erroneous dma_free_coherent in tmc_probe Mathieu Poirier
2016-06-30 16:22 ` Mathieu Poirier
2016-06-30 16:22 ` [PATCH 05/13] coresight: Consolidate error handling path for tmc_probe Mathieu Poirier
2016-06-30 16:22 ` Mathieu Poirier
2016-06-30 16:22 ` [PATCH 06/13] coresight: Fix csdev connections initialisation Mathieu Poirier
2016-06-30 16:22 ` Mathieu Poirier
2016-06-30 16:22 ` [PATCH 07/13] coresight: tmc: Limit the trace to available data Mathieu Poirier
2016-06-30 16:22 ` Mathieu Poirier
2016-06-30 16:22 ` [PATCH 08/13] coresight: etmv4: Fix ETMv4x peripheral ID table Mathieu Poirier
2016-06-30 16:22 ` Mathieu Poirier
2016-06-30 16:22 ` [PATCH 09/13] coresight: Cleanup TMC status check Mathieu Poirier
2016-06-30 16:22 ` Mathieu Poirier
2016-06-30 16:22 ` [PATCH 10/13] coresight: Add better messages for coresight_timeout Mathieu Poirier
2016-06-30 16:22 ` Mathieu Poirier
2016-06-30 16:22 ` [PATCH 11/13] coresight: delay initialisation when children are missing Mathieu Poirier
2016-06-30 16:22 ` Mathieu Poirier
2016-06-30 16:22 ` [PATCH 12/13] coresight: document binding acronyms Mathieu Poirier
2016-06-30 16:22 ` Mathieu Poirier
2016-06-30 16:22 ` Mathieu Poirier [this message]
2016-06-30 16:22 ` [PATCH 13/13] coresight: add PM runtime calls to coresight_simple_func() Mathieu Poirier
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