From: Marc Zyngier <marc.zyngier@arm.com> To: "Paolo Bonzini" <pbonzini@redhat.com>, "Radim Krčmář" <rkrcmar@redhat.com> Cc: Andre Przywara <andre.przywara@arm.com>, Eric Auger <eric.auger@redhat.com>, Christoffer Dall <christoffer.dall@linaro.org>, Dan Carpenter <dan.carpenter@oracle.com>, kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Subject: [PATCH 33/55] KVM: arm64: vgic: Handle ITS related GICv3 redistributor registers Date: Fri, 22 Jul 2016 18:28:50 +0100 [thread overview] Message-ID: <1469208552-4155-34-git-send-email-marc.zyngier@arm.com> (raw) In-Reply-To: <1469208552-4155-1-git-send-email-marc.zyngier@arm.com> From: Andre Przywara <andre.przywara@arm.com> In the GICv3 redistributor there are the PENDBASER and PROPBASER registers which we did not emulate so far, as they only make sense when having an ITS. In preparation for that emulate those MMIO accesses by storing the 64-bit data written into it into a variable which we later read in the ITS emulation. We also sanitise the registers, making sure RES0 regions are respected and checking for valid memory attributes. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Tested-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> --- include/kvm/arm_vgic.h | 13 ++++ virt/kvm/arm/vgic/vgic-mmio-v3.c | 153 ++++++++++++++++++++++++++++++++++++++- virt/kvm/arm/vgic/vgic-mmio.h | 8 ++ virt/kvm/arm/vgic/vgic-v3.c | 11 ++- 4 files changed, 181 insertions(+), 4 deletions(-) diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h index 450b4da..df2dec5 100644 --- a/include/kvm/arm_vgic.h +++ b/include/kvm/arm_vgic.h @@ -146,6 +146,14 @@ struct vgic_dist { struct vgic_irq *spis; struct vgic_io_device dist_iodev; + + /* + * Contains the attributes and gpa of the LPI configuration table. + * Since we report GICR_TYPER.CommonLPIAff as 0b00, we can share + * one address across all redistributors. + * GICv3 spec: 6.1.2 "LPI Configuration tables" + */ + u64 propbaser; }; struct vgic_v2_cpu_if { @@ -200,6 +208,11 @@ struct vgic_cpu { */ struct vgic_io_device rd_iodev; struct vgic_io_device sgi_iodev; + + /* Contains the attributes and gpa of the LPI pending tables. */ + u64 pendbaser; + + bool lpis_enabled; }; int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write); diff --git a/virt/kvm/arm/vgic/vgic-mmio-v3.c b/virt/kvm/arm/vgic/vgic-mmio-v3.c index bfcafbd..278bfbb 100644 --- a/virt/kvm/arm/vgic/vgic-mmio-v3.c +++ b/virt/kvm/arm/vgic/vgic-mmio-v3.c @@ -29,6 +29,19 @@ static unsigned long extract_bytes(unsigned long data, unsigned int offset, return (data >> (offset * 8)) & GENMASK_ULL(num * 8 - 1, 0); } +/* allows updates of any half of a 64-bit register (or the whole thing) */ +static u64 update_64bit_reg(u64 reg, unsigned int offset, unsigned int len, + unsigned long val) +{ + int lower = (offset & 4) * 8; + int upper = lower + 8 * len - 1; + + reg &= ~GENMASK_ULL(upper, lower); + val &= GENMASK_ULL(len * 8 - 1, 0); + + return reg | ((u64)val << lower); +} + static unsigned long vgic_mmio_read_v3_misc(struct kvm_vcpu *vcpu, gpa_t addr, unsigned int len) { @@ -152,6 +165,142 @@ static unsigned long vgic_mmio_read_v3_idregs(struct kvm_vcpu *vcpu, return 0; } +/* We want to avoid outer shareable. */ +u64 vgic_sanitise_shareability(u64 field) +{ + switch (field) { + case GIC_BASER_OuterShareable: + return GIC_BASER_InnerShareable; + default: + return field; + } +} + +/* Avoid any inner non-cacheable mapping. */ +u64 vgic_sanitise_inner_cacheability(u64 field) +{ + switch (field) { + case GIC_BASER_CACHE_nCnB: + case GIC_BASER_CACHE_nC: + return GIC_BASER_CACHE_RaWb; + default: + return field; + } +} + +/* Non-cacheable or same-as-inner are OK. */ +u64 vgic_sanitise_outer_cacheability(u64 field) +{ + switch (field) { + case GIC_BASER_CACHE_SameAsInner: + case GIC_BASER_CACHE_nC: + return field; + default: + return GIC_BASER_CACHE_nC; + } +} + +u64 vgic_sanitise_field(u64 reg, u64 field_mask, int field_shift, + u64 (*sanitise_fn)(u64)) +{ + u64 field = (reg & field_mask) >> field_shift; + + field = sanitise_fn(field) << field_shift; + return (reg & ~field_mask) | field; +} + +#define PROPBASER_RES0_MASK \ + (GENMASK_ULL(63, 59) | GENMASK_ULL(55, 52) | GENMASK_ULL(6, 5)) +#define PENDBASER_RES0_MASK \ + (BIT_ULL(63) | GENMASK_ULL(61, 59) | GENMASK_ULL(55, 52) | \ + GENMASK_ULL(15, 12) | GENMASK_ULL(6, 0)) + +static u64 vgic_sanitise_pendbaser(u64 reg) +{ + reg = vgic_sanitise_field(reg, GICR_PENDBASER_SHAREABILITY_MASK, + GICR_PENDBASER_SHAREABILITY_SHIFT, + vgic_sanitise_shareability); + reg = vgic_sanitise_field(reg, GICR_PENDBASER_INNER_CACHEABILITY_MASK, + GICR_PENDBASER_INNER_CACHEABILITY_SHIFT, + vgic_sanitise_inner_cacheability); + reg = vgic_sanitise_field(reg, GICR_PENDBASER_OUTER_CACHEABILITY_MASK, + GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT, + vgic_sanitise_outer_cacheability); + + reg &= ~PENDBASER_RES0_MASK; + reg &= ~GENMASK_ULL(51, 48); + + return reg; +} + +static u64 vgic_sanitise_propbaser(u64 reg) +{ + reg = vgic_sanitise_field(reg, GICR_PROPBASER_SHAREABILITY_MASK, + GICR_PROPBASER_SHAREABILITY_SHIFT, + vgic_sanitise_shareability); + reg = vgic_sanitise_field(reg, GICR_PROPBASER_INNER_CACHEABILITY_MASK, + GICR_PROPBASER_INNER_CACHEABILITY_SHIFT, + vgic_sanitise_inner_cacheability); + reg = vgic_sanitise_field(reg, GICR_PROPBASER_OUTER_CACHEABILITY_MASK, + GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT, + vgic_sanitise_outer_cacheability); + + reg &= ~PROPBASER_RES0_MASK; + reg &= ~GENMASK_ULL(51, 48); + return reg; +} + +static unsigned long vgic_mmio_read_propbase(struct kvm_vcpu *vcpu, + gpa_t addr, unsigned int len) +{ + struct vgic_dist *dist = &vcpu->kvm->arch.vgic; + + return extract_bytes(dist->propbaser, addr & 7, len); +} + +static void vgic_mmio_write_propbase(struct kvm_vcpu *vcpu, + gpa_t addr, unsigned int len, + unsigned long val) +{ + struct vgic_dist *dist = &vcpu->kvm->arch.vgic; + struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; + u64 propbaser = dist->propbaser; + + /* Storing a value with LPIs already enabled is undefined */ + if (vgic_cpu->lpis_enabled) + return; + + propbaser = update_64bit_reg(propbaser, addr & 4, len, val); + propbaser = vgic_sanitise_propbaser(propbaser); + + dist->propbaser = propbaser; +} + +static unsigned long vgic_mmio_read_pendbase(struct kvm_vcpu *vcpu, + gpa_t addr, unsigned int len) +{ + struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; + + return extract_bytes(vgic_cpu->pendbaser, addr & 7, len); +} + +static void vgic_mmio_write_pendbase(struct kvm_vcpu *vcpu, + gpa_t addr, unsigned int len, + unsigned long val) +{ + struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; + u64 pendbaser = vgic_cpu->pendbaser; + + /* Storing a value with LPIs already enabled is undefined */ + if (vgic_cpu->lpis_enabled) + return; + + pendbaser = update_64bit_reg(pendbaser, addr & 4, len, val); + pendbaser = vgic_sanitise_pendbaser(pendbaser); + + vgic_cpu->pendbaser = pendbaser; +} + /* * The GICv3 per-IRQ registers are split to control PPIs and SGIs in the * redistributors, while SPIs are covered by registers in the distributor @@ -232,10 +381,10 @@ static const struct vgic_register_region vgic_v3_rdbase_registers[] = { vgic_mmio_read_v3r_typer, vgic_mmio_write_wi, 8, VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), REGISTER_DESC_WITH_LENGTH(GICR_PROPBASER, - vgic_mmio_read_raz, vgic_mmio_write_wi, 8, + vgic_mmio_read_propbase, vgic_mmio_write_propbase, 8, VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), REGISTER_DESC_WITH_LENGTH(GICR_PENDBASER, - vgic_mmio_read_raz, vgic_mmio_write_wi, 8, + vgic_mmio_read_pendbase, vgic_mmio_write_pendbase, 8, VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), REGISTER_DESC_WITH_LENGTH(GICR_IDREGS, vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48, diff --git a/virt/kvm/arm/vgic/vgic-mmio.h b/virt/kvm/arm/vgic/vgic-mmio.h index 8509014..71aa39d 100644 --- a/virt/kvm/arm/vgic/vgic-mmio.h +++ b/virt/kvm/arm/vgic/vgic-mmio.h @@ -147,4 +147,12 @@ unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev); unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev); +#ifdef CONFIG_KVM_ARM_VGIC_V3 +u64 vgic_sanitise_outer_cacheability(u64 reg); +u64 vgic_sanitise_inner_cacheability(u64 reg); +u64 vgic_sanitise_shareability(u64 reg); +u64 vgic_sanitise_field(u64 reg, u64 field_mask, int field_shift, + u64 (*sanitise_fn)(u64)); +#endif + #endif diff --git a/virt/kvm/arm/vgic/vgic-v3.c b/virt/kvm/arm/vgic/vgic-v3.c index f0ac064..6f8f31f 100644 --- a/virt/kvm/arm/vgic/vgic-v3.c +++ b/virt/kvm/arm/vgic/vgic-v3.c @@ -191,6 +191,11 @@ void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp) vmcrp->pmr = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT; } +#define INITIAL_PENDBASER_VALUE \ + (GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWb) | \ + GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, SameAsInner) | \ + GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable)) + void vgic_v3_enable(struct kvm_vcpu *vcpu) { struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3; @@ -208,10 +213,12 @@ void vgic_v3_enable(struct kvm_vcpu *vcpu) * way, so we force SRE to 1 to demonstrate this to the guest. * This goes with the spec allowing the value to be RAO/WI. */ - if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) + if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) { vgic_v3->vgic_sre = ICC_SRE_EL1_SRE; - else + vcpu->arch.vgic_cpu.pendbaser = INITIAL_PENDBASER_VALUE; + } else { vgic_v3->vgic_sre = 0; + } /* Get the show on the road... */ vgic_v3->vgic_hcr = ICH_HCR_EN; -- 2.8.1
WARNING: multiple messages have this Message-ID (diff)
From: marc.zyngier@arm.com (Marc Zyngier) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 33/55] KVM: arm64: vgic: Handle ITS related GICv3 redistributor registers Date: Fri, 22 Jul 2016 18:28:50 +0100 [thread overview] Message-ID: <1469208552-4155-34-git-send-email-marc.zyngier@arm.com> (raw) In-Reply-To: <1469208552-4155-1-git-send-email-marc.zyngier@arm.com> From: Andre Przywara <andre.przywara@arm.com> In the GICv3 redistributor there are the PENDBASER and PROPBASER registers which we did not emulate so far, as they only make sense when having an ITS. In preparation for that emulate those MMIO accesses by storing the 64-bit data written into it into a variable which we later read in the ITS emulation. We also sanitise the registers, making sure RES0 regions are respected and checking for valid memory attributes. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Tested-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> --- include/kvm/arm_vgic.h | 13 ++++ virt/kvm/arm/vgic/vgic-mmio-v3.c | 153 ++++++++++++++++++++++++++++++++++++++- virt/kvm/arm/vgic/vgic-mmio.h | 8 ++ virt/kvm/arm/vgic/vgic-v3.c | 11 ++- 4 files changed, 181 insertions(+), 4 deletions(-) diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h index 450b4da..df2dec5 100644 --- a/include/kvm/arm_vgic.h +++ b/include/kvm/arm_vgic.h @@ -146,6 +146,14 @@ struct vgic_dist { struct vgic_irq *spis; struct vgic_io_device dist_iodev; + + /* + * Contains the attributes and gpa of the LPI configuration table. + * Since we report GICR_TYPER.CommonLPIAff as 0b00, we can share + * one address across all redistributors. + * GICv3 spec: 6.1.2 "LPI Configuration tables" + */ + u64 propbaser; }; struct vgic_v2_cpu_if { @@ -200,6 +208,11 @@ struct vgic_cpu { */ struct vgic_io_device rd_iodev; struct vgic_io_device sgi_iodev; + + /* Contains the attributes and gpa of the LPI pending tables. */ + u64 pendbaser; + + bool lpis_enabled; }; int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write); diff --git a/virt/kvm/arm/vgic/vgic-mmio-v3.c b/virt/kvm/arm/vgic/vgic-mmio-v3.c index bfcafbd..278bfbb 100644 --- a/virt/kvm/arm/vgic/vgic-mmio-v3.c +++ b/virt/kvm/arm/vgic/vgic-mmio-v3.c @@ -29,6 +29,19 @@ static unsigned long extract_bytes(unsigned long data, unsigned int offset, return (data >> (offset * 8)) & GENMASK_ULL(num * 8 - 1, 0); } +/* allows updates of any half of a 64-bit register (or the whole thing) */ +static u64 update_64bit_reg(u64 reg, unsigned int offset, unsigned int len, + unsigned long val) +{ + int lower = (offset & 4) * 8; + int upper = lower + 8 * len - 1; + + reg &= ~GENMASK_ULL(upper, lower); + val &= GENMASK_ULL(len * 8 - 1, 0); + + return reg | ((u64)val << lower); +} + static unsigned long vgic_mmio_read_v3_misc(struct kvm_vcpu *vcpu, gpa_t addr, unsigned int len) { @@ -152,6 +165,142 @@ static unsigned long vgic_mmio_read_v3_idregs(struct kvm_vcpu *vcpu, return 0; } +/* We want to avoid outer shareable. */ +u64 vgic_sanitise_shareability(u64 field) +{ + switch (field) { + case GIC_BASER_OuterShareable: + return GIC_BASER_InnerShareable; + default: + return field; + } +} + +/* Avoid any inner non-cacheable mapping. */ +u64 vgic_sanitise_inner_cacheability(u64 field) +{ + switch (field) { + case GIC_BASER_CACHE_nCnB: + case GIC_BASER_CACHE_nC: + return GIC_BASER_CACHE_RaWb; + default: + return field; + } +} + +/* Non-cacheable or same-as-inner are OK. */ +u64 vgic_sanitise_outer_cacheability(u64 field) +{ + switch (field) { + case GIC_BASER_CACHE_SameAsInner: + case GIC_BASER_CACHE_nC: + return field; + default: + return GIC_BASER_CACHE_nC; + } +} + +u64 vgic_sanitise_field(u64 reg, u64 field_mask, int field_shift, + u64 (*sanitise_fn)(u64)) +{ + u64 field = (reg & field_mask) >> field_shift; + + field = sanitise_fn(field) << field_shift; + return (reg & ~field_mask) | field; +} + +#define PROPBASER_RES0_MASK \ + (GENMASK_ULL(63, 59) | GENMASK_ULL(55, 52) | GENMASK_ULL(6, 5)) +#define PENDBASER_RES0_MASK \ + (BIT_ULL(63) | GENMASK_ULL(61, 59) | GENMASK_ULL(55, 52) | \ + GENMASK_ULL(15, 12) | GENMASK_ULL(6, 0)) + +static u64 vgic_sanitise_pendbaser(u64 reg) +{ + reg = vgic_sanitise_field(reg, GICR_PENDBASER_SHAREABILITY_MASK, + GICR_PENDBASER_SHAREABILITY_SHIFT, + vgic_sanitise_shareability); + reg = vgic_sanitise_field(reg, GICR_PENDBASER_INNER_CACHEABILITY_MASK, + GICR_PENDBASER_INNER_CACHEABILITY_SHIFT, + vgic_sanitise_inner_cacheability); + reg = vgic_sanitise_field(reg, GICR_PENDBASER_OUTER_CACHEABILITY_MASK, + GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT, + vgic_sanitise_outer_cacheability); + + reg &= ~PENDBASER_RES0_MASK; + reg &= ~GENMASK_ULL(51, 48); + + return reg; +} + +static u64 vgic_sanitise_propbaser(u64 reg) +{ + reg = vgic_sanitise_field(reg, GICR_PROPBASER_SHAREABILITY_MASK, + GICR_PROPBASER_SHAREABILITY_SHIFT, + vgic_sanitise_shareability); + reg = vgic_sanitise_field(reg, GICR_PROPBASER_INNER_CACHEABILITY_MASK, + GICR_PROPBASER_INNER_CACHEABILITY_SHIFT, + vgic_sanitise_inner_cacheability); + reg = vgic_sanitise_field(reg, GICR_PROPBASER_OUTER_CACHEABILITY_MASK, + GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT, + vgic_sanitise_outer_cacheability); + + reg &= ~PROPBASER_RES0_MASK; + reg &= ~GENMASK_ULL(51, 48); + return reg; +} + +static unsigned long vgic_mmio_read_propbase(struct kvm_vcpu *vcpu, + gpa_t addr, unsigned int len) +{ + struct vgic_dist *dist = &vcpu->kvm->arch.vgic; + + return extract_bytes(dist->propbaser, addr & 7, len); +} + +static void vgic_mmio_write_propbase(struct kvm_vcpu *vcpu, + gpa_t addr, unsigned int len, + unsigned long val) +{ + struct vgic_dist *dist = &vcpu->kvm->arch.vgic; + struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; + u64 propbaser = dist->propbaser; + + /* Storing a value with LPIs already enabled is undefined */ + if (vgic_cpu->lpis_enabled) + return; + + propbaser = update_64bit_reg(propbaser, addr & 4, len, val); + propbaser = vgic_sanitise_propbaser(propbaser); + + dist->propbaser = propbaser; +} + +static unsigned long vgic_mmio_read_pendbase(struct kvm_vcpu *vcpu, + gpa_t addr, unsigned int len) +{ + struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; + + return extract_bytes(vgic_cpu->pendbaser, addr & 7, len); +} + +static void vgic_mmio_write_pendbase(struct kvm_vcpu *vcpu, + gpa_t addr, unsigned int len, + unsigned long val) +{ + struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; + u64 pendbaser = vgic_cpu->pendbaser; + + /* Storing a value with LPIs already enabled is undefined */ + if (vgic_cpu->lpis_enabled) + return; + + pendbaser = update_64bit_reg(pendbaser, addr & 4, len, val); + pendbaser = vgic_sanitise_pendbaser(pendbaser); + + vgic_cpu->pendbaser = pendbaser; +} + /* * The GICv3 per-IRQ registers are split to control PPIs and SGIs in the * redistributors, while SPIs are covered by registers in the distributor @@ -232,10 +381,10 @@ static const struct vgic_register_region vgic_v3_rdbase_registers[] = { vgic_mmio_read_v3r_typer, vgic_mmio_write_wi, 8, VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), REGISTER_DESC_WITH_LENGTH(GICR_PROPBASER, - vgic_mmio_read_raz, vgic_mmio_write_wi, 8, + vgic_mmio_read_propbase, vgic_mmio_write_propbase, 8, VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), REGISTER_DESC_WITH_LENGTH(GICR_PENDBASER, - vgic_mmio_read_raz, vgic_mmio_write_wi, 8, + vgic_mmio_read_pendbase, vgic_mmio_write_pendbase, 8, VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), REGISTER_DESC_WITH_LENGTH(GICR_IDREGS, vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48, diff --git a/virt/kvm/arm/vgic/vgic-mmio.h b/virt/kvm/arm/vgic/vgic-mmio.h index 8509014..71aa39d 100644 --- a/virt/kvm/arm/vgic/vgic-mmio.h +++ b/virt/kvm/arm/vgic/vgic-mmio.h @@ -147,4 +147,12 @@ unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev); unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev); +#ifdef CONFIG_KVM_ARM_VGIC_V3 +u64 vgic_sanitise_outer_cacheability(u64 reg); +u64 vgic_sanitise_inner_cacheability(u64 reg); +u64 vgic_sanitise_shareability(u64 reg); +u64 vgic_sanitise_field(u64 reg, u64 field_mask, int field_shift, + u64 (*sanitise_fn)(u64)); +#endif + #endif diff --git a/virt/kvm/arm/vgic/vgic-v3.c b/virt/kvm/arm/vgic/vgic-v3.c index f0ac064..6f8f31f 100644 --- a/virt/kvm/arm/vgic/vgic-v3.c +++ b/virt/kvm/arm/vgic/vgic-v3.c @@ -191,6 +191,11 @@ void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp) vmcrp->pmr = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT; } +#define INITIAL_PENDBASER_VALUE \ + (GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWb) | \ + GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, SameAsInner) | \ + GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable)) + void vgic_v3_enable(struct kvm_vcpu *vcpu) { struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3; @@ -208,10 +213,12 @@ void vgic_v3_enable(struct kvm_vcpu *vcpu) * way, so we force SRE to 1 to demonstrate this to the guest. * This goes with the spec allowing the value to be RAO/WI. */ - if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) + if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) { vgic_v3->vgic_sre = ICC_SRE_EL1_SRE; - else + vcpu->arch.vgic_cpu.pendbaser = INITIAL_PENDBASER_VALUE; + } else { vgic_v3->vgic_sre = 0; + } /* Get the show on the road... */ vgic_v3->vgic_hcr = ICH_HCR_EN; -- 2.8.1
next prev parent reply other threads:[~2016-07-22 17:30 UTC|newest] Thread overview: 134+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-07-22 17:28 [PULL] KVM/ARM updates for Linux 4.8, take #1 Marc Zyngier 2016-07-22 17:28 ` Marc Zyngier 2016-07-22 17:28 ` [PATCH 01/55] arm/arm64: KVM: Add a protection parameter to create_hyp_mappings Marc Zyngier 2016-07-22 17:28 ` Marc Zyngier 2016-07-22 17:28 ` [PATCH 02/55] arm64: Add PTE_HYP_XN page table flag Marc Zyngier 2016-07-22 17:28 ` Marc Zyngier 2016-07-22 17:28 ` [PATCH 03/55] arm/arm64: KVM: Enforce HYP read-only mapping of the kernel's rodata section Marc Zyngier 2016-07-22 17:28 ` Marc Zyngier 2016-07-22 17:28 ` [PATCH 04/55] arm/arm64: KVM: Map the HYP text as read-only Marc Zyngier 2016-07-22 17:28 ` Marc Zyngier 2016-07-22 17:28 ` [PATCH 05/55] arm/arm64: KVM: Make default HYP mappings non-excutable Marc Zyngier 2016-07-22 17:28 ` Marc Zyngier 2016-07-22 17:28 ` [PATCH 06/55] KVM: arm/arm64: The GIC is dead, long live the GIC Marc Zyngier 2016-07-22 17:28 ` Marc Zyngier 2016-07-22 17:28 ` [PATCH 07/55] arm64: KVM: Merged page tables documentation Marc Zyngier 2016-07-22 17:28 ` Marc Zyngier 2016-07-22 17:28 ` [PATCH 08/55] arm64: KVM: Always reference __hyp_panic_string via its kernel VA Marc Zyngier 2016-07-22 17:28 ` Marc Zyngier 2016-07-22 17:28 ` [PATCH 09/55] arm/arm64: KVM: Remove hyp_kern_va helper Marc Zyngier 2016-07-22 17:28 ` Marc Zyngier 2016-07-22 17:28 ` [PATCH 10/55] arm64: KVM: Kill HYP_PAGE_OFFSET Marc Zyngier 2016-07-22 17:28 ` Marc Zyngier 2016-07-22 17:28 ` [PATCH 11/55] arm64: Add ARM64_HYP_OFFSET_LOW capability Marc Zyngier 2016-07-22 17:28 ` Marc Zyngier 2016-07-22 17:28 ` [PATCH 12/55] arm64: KVM: Define HYP offset masks Marc Zyngier 2016-07-22 17:28 ` Marc Zyngier 2016-07-22 17:28 ` [PATCH 13/55] arm64: KVM: Refactor kern_hyp_va to deal with multiple offsets Marc Zyngier 2016-07-22 17:28 ` Marc Zyngier 2016-07-22 17:28 ` [PATCH 14/55] arm/arm64: KVM: Export __hyp_text_start/end symbols Marc Zyngier 2016-07-22 17:28 ` Marc Zyngier 2016-07-22 17:28 ` [PATCH 15/55] arm64: KVM: Runtime detection of lower HYP offset Marc Zyngier 2016-07-22 17:28 ` Marc Zyngier 2016-07-22 17:28 ` [PATCH 16/55] arm/arm64: KVM: Always have merged page tables Marc Zyngier 2016-07-22 17:28 ` Marc Zyngier 2016-07-22 17:28 ` [PATCH 17/55] arm64: KVM: Simplify HYP init/teardown Marc Zyngier 2016-07-22 17:28 ` Marc Zyngier 2016-07-22 17:28 ` [PATCH 18/55] arm/arm64: KVM: Drop boot_pgd Marc Zyngier 2016-07-22 17:28 ` Marc Zyngier 2016-07-22 17:28 ` [PATCH 19/55] arm/arm64: KVM: Kill free_boot_hyp_pgd Marc Zyngier 2016-07-22 17:28 ` Marc Zyngier 2016-07-22 17:28 ` [PATCH 20/55] arm: KVM: Simplify HYP init Marc Zyngier 2016-07-22 17:28 ` Marc Zyngier 2016-07-22 17:28 ` [PATCH 21/55] arm: KVM: Allow hyp teardown Marc Zyngier 2016-07-22 17:28 ` Marc Zyngier 2016-07-22 17:28 ` [PATCH 22/55] arm/arm64: KVM: Prune unused #defines Marc Zyngier 2016-07-22 17:28 ` Marc Zyngier 2016-07-22 17:28 ` [PATCH 23/55] arm/arm64: KVM: Check that IDMAP doesn't intersect with VA range Marc Zyngier 2016-07-22 17:28 ` Marc Zyngier 2016-07-22 17:28 ` [PATCH 24/55] arm/arm64: Get rid of KERN_TO_HYP Marc Zyngier 2016-07-22 17:28 ` Marc Zyngier 2016-07-22 17:28 ` [PATCH 25/55] arm64: KVM: Clean up a condition Marc Zyngier 2016-07-22 17:28 ` Marc Zyngier 2016-07-22 17:28 ` [PATCH 26/55] KVM: arm/arm64: vgic: Move redistributor kvm_io_devices Marc Zyngier 2016-07-22 17:28 ` Marc Zyngier 2016-07-22 17:28 ` [PATCH 27/55] KVM: arm/arm64: vgic: Check return value for kvm_register_vgic_device Marc Zyngier 2016-07-22 17:28 ` Marc Zyngier 2016-07-22 17:28 ` [PATCH 28/55] KVM: Extend struct kvm_msi to hold a 32-bit device ID Marc Zyngier 2016-07-22 17:28 ` Marc Zyngier 2016-07-22 17:28 ` [PATCH 29/55] KVM: arm/arm64: Extend arch CAP checks to allow per-VM capabilities Marc Zyngier 2016-07-22 17:28 ` Marc Zyngier 2016-07-22 17:28 ` [PATCH 30/55] KVM: kvm_io_bus: Add kvm_io_bus_get_dev() call Marc Zyngier 2016-07-22 17:28 ` Marc Zyngier 2016-07-22 17:28 ` [PATCH 31/55] KVM: arm/arm64: vgic: Add refcounting for IRQs Marc Zyngier 2016-07-22 17:28 ` Marc Zyngier 2016-07-22 17:28 ` [PATCH 32/55] irqchip/gic-v3: Refactor and add GICv3 definitions Marc Zyngier 2016-07-22 17:28 ` Marc Zyngier 2016-07-22 17:28 ` Marc Zyngier [this message] 2016-07-22 17:28 ` [PATCH 33/55] KVM: arm64: vgic: Handle ITS related GICv3 redistributor registers Marc Zyngier 2016-08-01 18:20 ` Christoffer Dall 2016-08-01 18:20 ` Christoffer Dall 2016-08-02 9:40 ` Andre Przywara 2016-08-02 9:40 ` Andre Przywara 2016-08-02 10:12 ` Marc Zyngier 2016-08-02 10:12 ` Marc Zyngier 2016-08-02 14:33 ` Christoffer Dall 2016-08-02 14:33 ` Christoffer Dall 2016-08-02 14:46 ` Marc Zyngier 2016-08-02 14:46 ` Marc Zyngier 2016-08-02 14:55 ` Christoffer Dall 2016-08-02 14:55 ` Christoffer Dall 2016-08-02 15:01 ` Marc Zyngier 2016-08-02 15:01 ` Marc Zyngier 2016-07-22 17:28 ` [PATCH 34/55] KVM: arm64: vgic-its: Introduce ITS emulation file with MMIO framework Marc Zyngier 2016-07-22 17:28 ` Marc Zyngier 2016-07-22 17:28 ` [PATCH 35/55] KVM: arm64: vgic-its: Introduce new KVM ITS device Marc Zyngier 2016-07-22 17:28 ` Marc Zyngier 2016-07-22 17:28 ` [PATCH 36/55] KVM: arm64: vgic-its: Implement basic ITS register handlers Marc Zyngier 2016-07-22 17:28 ` Marc Zyngier 2016-07-22 17:28 ` [PATCH 37/55] KVM: arm64: vgic-its: Connect LPIs to the VGIC emulation Marc Zyngier 2016-07-22 17:28 ` Marc Zyngier 2016-07-22 17:28 ` [PATCH 38/55] KVM: arm64: vgic-its: Read initial LPI pending table Marc Zyngier 2016-07-22 17:28 ` Marc Zyngier 2016-07-22 17:28 ` [PATCH 39/55] KVM: arm64: vgic-its: Allow updates of LPI configuration table Marc Zyngier 2016-07-22 17:28 ` Marc Zyngier 2016-07-22 17:28 ` [PATCH 40/55] KVM: arm64: vgic-its: Implement ITS command queue command handlers Marc Zyngier 2016-07-22 17:28 ` Marc Zyngier 2016-07-22 17:28 ` [PATCH 41/55] KVM: arm64: vgic-its: Implement MSI injection in ITS emulation Marc Zyngier 2016-07-22 17:28 ` Marc Zyngier 2016-08-01 18:20 ` Christoffer Dall 2016-08-01 18:20 ` Christoffer Dall 2016-08-02 10:18 ` Marc Zyngier 2016-08-02 10:18 ` Marc Zyngier 2016-08-04 10:47 ` Christoffer Dall 2016-08-04 10:47 ` Christoffer Dall 2016-07-22 17:28 ` [PATCH 42/55] KVM: arm64: vgic-its: Enable ITS emulation as a virtual MSI controller Marc Zyngier 2016-07-22 17:28 ` Marc Zyngier 2016-07-22 17:29 ` [PATCH 43/55] KVM: arm/arm64: Fix vGICv2 KVM_DEV_ARM_VGIC_GRP_CPU/DIST_REGS Marc Zyngier 2016-07-22 17:29 ` Marc Zyngier 2016-07-22 17:29 ` [PATCH 44/55] irqchip/gicv3-its: Restore all cacheability attributes Marc Zyngier 2016-07-22 17:29 ` Marc Zyngier 2016-07-22 17:29 ` [PATCH 45/55] KVM: arm64: vgic-its: Generalize use of vgic_get_irq_kref Marc Zyngier 2016-07-22 17:29 ` Marc Zyngier 2016-07-22 17:29 ` [PATCH 46/55] KVM: arm64: vgic-its: Fix handling of indirect tables Marc Zyngier 2016-07-22 17:29 ` Marc Zyngier 2016-07-22 17:29 ` [PATCH 47/55] KVM: arm64: vgic-its: Fix vgic_its_check_device_id BE handling Marc Zyngier 2016-07-22 17:29 ` Marc Zyngier 2016-07-22 17:29 ` [PATCH 48/55] KVM: arm64: vgic-its: Fix misleading nr_entries in vgic_its_check_device_id Marc Zyngier 2016-07-22 17:29 ` Marc Zyngier 2016-07-22 17:29 ` [PATCH 49/55] KVM: arm64: vgic-its: Validate the device table L1 entry Marc Zyngier 2016-07-22 17:29 ` Marc Zyngier 2016-07-22 17:29 ` [PATCH 50/55] KVM: arm64: vgic-its: Fix L2 entry validation for indirect tables Marc Zyngier 2016-07-22 17:29 ` Marc Zyngier 2016-07-22 17:29 ` [PATCH 51/55] KVM: arm64: vgic-its: Add collection allocator/destructor Marc Zyngier 2016-07-22 17:29 ` Marc Zyngier 2016-07-22 17:29 ` [PATCH 52/55] KVM: arm64: vgic-its: Add pointer to corresponding kvm_device Marc Zyngier 2016-07-22 17:29 ` Marc Zyngier 2016-07-22 17:29 ` [PATCH 53/55] KVM: arm64: vgic-its: Turn device_id validation into generic ID validation Marc Zyngier 2016-07-22 17:29 ` Marc Zyngier 2016-07-22 17:29 ` [PATCH 54/55] KVM: arm64: vgic-its: Make vgic_its_cmd_handle_mapi similar to other handlers Marc Zyngier 2016-07-22 17:29 ` Marc Zyngier 2016-07-22 17:29 ` [PATCH 55/55] KVM: arm64: vgic-its: Simplify MAPI error handling Marc Zyngier 2016-07-22 17:29 ` Marc Zyngier 2016-07-22 19:50 ` [PULL] KVM/ARM updates for Linux 4.8, take #1 Radim Krčmář 2016-07-22 19:50 ` Radim Krčmář
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