From: Xing Zheng <zhengxing@rock-chips.com>
To: heiko@sntech.de
Cc: linux-rockchip@lists.infradead.org, dianders@chromium.org,
briannorris@chromium.org, huangtao@rock-chips.com,
zhangqing@rock-chips.com, Xing Zheng <zhengxing@rock-chips.com>,
frank.wang@rock-chips.com, wulf@rock-chips.com,
Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Ian Campbell <ijc+devicetree@hellion.org.uk>,
Kumar Gala <galak@codeaurora.org>,
Jianqun Xu <jay.xu@rock-chips.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH 1/6] clk: rockchip: rk3399: export USBPHYx_480M_SRC clock IDs
Date: Mon, 1 Aug 2016 11:37:19 +0800 [thread overview]
Message-ID: <1470022644-2152-2-git-send-email-zhengxing@rock-chips.com> (raw)
In-Reply-To: <1470022644-2152-1-git-send-email-zhengxing@rock-chips.com>
We export some clock IDs for the usb phy 480m source clocks.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
---
include/dt-bindings/clock/rk3399-cru.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h
index 50a44cf..c4d8311 100644
--- a/include/dt-bindings/clock/rk3399-cru.h
+++ b/include/dt-bindings/clock/rk3399-cru.h
@@ -131,6 +131,8 @@
#define SCLK_DPHY_RX0_CFG 165
#define SCLK_RMII_SRC 166
#define SCLK_PCIEPHY_REF100M 167
+#define SCLK_USBPHY0_480M_SRC 168
+#define SCLK_USBPHY1_480M_SRC 169
#define DCLK_VOP0 180
#define DCLK_VOP1 181
--
1.7.9.5
WARNING: multiple messages have this Message-ID (diff)
From: Xing Zheng <zhengxing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
To: heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org
Cc: huangtao-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
zhangqing-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>,
Xing Zheng <zhengxing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>,
Ian Campbell
<ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>,
briannorris-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org,
dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
wulf-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
Jianqun Xu <jay.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Subject: [PATCH 1/6] clk: rockchip: rk3399: export USBPHYx_480M_SRC clock IDs
Date: Mon, 1 Aug 2016 11:37:19 +0800 [thread overview]
Message-ID: <1470022644-2152-2-git-send-email-zhengxing@rock-chips.com> (raw)
In-Reply-To: <1470022644-2152-1-git-send-email-zhengxing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
We export some clock IDs for the usb phy 480m source clocks.
Signed-off-by: Xing Zheng <zhengxing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
include/dt-bindings/clock/rk3399-cru.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h
index 50a44cf..c4d8311 100644
--- a/include/dt-bindings/clock/rk3399-cru.h
+++ b/include/dt-bindings/clock/rk3399-cru.h
@@ -131,6 +131,8 @@
#define SCLK_DPHY_RX0_CFG 165
#define SCLK_RMII_SRC 166
#define SCLK_PCIEPHY_REF100M 167
+#define SCLK_USBPHY0_480M_SRC 168
+#define SCLK_USBPHY1_480M_SRC 169
#define DCLK_VOP0 180
#define DCLK_VOP1 181
--
1.7.9.5
next prev parent reply other threads:[~2016-08-01 3:48 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-01 3:37 [PATCH 0/6] fix and optimize some clock configuration for the RK3399 platfom Xing Zheng
2016-08-01 3:37 ` Xing Zheng
2016-08-01 3:37 ` Xing Zheng
2016-08-01 3:37 ` Xing Zheng [this message]
2016-08-01 3:37 ` [PATCH 1/6] clk: rockchip: rk3399: export USBPHYx_480M_SRC clock IDs Xing Zheng
2016-08-01 3:37 ` [PATCH 2/6] clk: rockchip: rk3399: export 480M_SRC clock id for usbphy0/usbphy1 Xing Zheng
2016-08-01 3:37 ` Xing Zheng
2016-08-01 3:37 ` Xing Zheng
2016-08-01 3:37 ` [PATCH 3/6] clk: rockchip: rk3399: fix incorrect aclk_emmc source gate bits Xing Zheng
2016-08-01 3:37 ` Xing Zheng
2016-08-01 3:37 ` Xing Zheng
2016-08-01 3:37 ` [PATCH 4/6] clk: rockchip: rk3399: add 65MHz and 106.5MHz clocks for HDMI Xing Zheng
2016-08-01 3:37 ` Xing Zheng
2016-08-01 3:37 ` Xing Zheng
2016-08-01 3:46 ` [PATCH 5/6] clk: rockchip: rk3399: delete the CLK_IGNORE_UNUSED for aclk_pcie Xing Zheng
2016-08-01 3:46 ` Xing Zheng
2016-08-01 3:46 ` Xing Zheng
2016-08-01 3:46 ` [PATCH 6/6] clk: rockchip: rk3399: Add support frac mode frequencies Xing Zheng
2016-08-01 3:46 ` Xing Zheng
2016-08-01 3:46 ` Xing Zheng
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