From: Jerome Brunet <jbrunet@baylibre.com>
To: Carlo Caione <carlo@caione.org>,
Kevin Hilman <khilman@baylibre.com>,
Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
Marc Zyngier <marc.zyngier@arm.com>,
Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org,
Catalin Marinas <catalin.marinas@arm.com>,
Linus Walleij <linus.walleij@linaro.org>,
Will Deacon <will.deacon@arm.com>,
linux-kernel@vger.kernel.org,
Russell King <linux@armlinux.org.uk>,
linux-gpio@vger.kernel.org, linux-amlogic@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
Jerome Brunet <jbrunet@baylibre.com>
Subject: [PATCH 2/9] dt-bindings: interrupt-controller: add DT binding for meson GPIO interrupt controller
Date: Wed, 19 Oct 2016 12:08:22 +0200 [thread overview]
Message-ID: <1476871709-8359-3-git-send-email-jbrunet@baylibre.com> (raw)
In-Reply-To: <1476871709-8359-1-git-send-email-jbrunet@baylibre.com>
This commit adds the device tree bindings description for Amlogic's GPIO
interrupt controller available on the meson8, meson8b and gxbb SoC families
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
Rob, I did not include the Ack you gave for the RFC as bindings have slightly
changed. Only the interrupt property has be removed following a discussion I
had with Marc.
.../amlogic,meson-gpio-intc.txt | 31 ++++++++++++++++++++++
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
new file mode 100644
index 000000000000..2464d9a0865d
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
@@ -0,0 +1,31 @@
+Amlogic meson GPIO interrupt controller
+
+Meson SoCs contains an interrupt controller which is able watch the SoC pads
+and generate an interrupt on edges or level. The controller is essentially a
+256 pads to 8 GIC interrupt multiplexer, with a filter block to select edge
+or level and polarity. We don’t expose all 256 mux inputs because the
+documentation shows that upper part is not mapped to any pad. The actual number
+of interrupt exposed depends on the SoC.
+
+Required properties:
+
+- compatible : should be either
+ "amlogic,meson8-gpio-intc” for meson8 SoCs (AML7826MX) or
+ “amlogic,meson8b-gpio-intc” for meson8b SoCs (S805) or
+ “amlogic,meson-gxbb-gpio-intc” for GXBB SoCs (S905)
+- interrupt-parent : a phandle to the GIC the interrupts are routed to.
+ Usually this is provided at the root level of the device tree as it is
+ common to most of the SoC
+- reg : Specifies base physical address and size of the registers.
+- interrupt-controller : Identifies the node as an interrupt controller.
+- #interrupt-cells : Specifies the number of cells needed to encode an
+ interrupt source. The value must be 2.
+
+Example:
+
+gpio_interrupt: interrupt-controller@9880 {
+ compatible = "amlogic,meson-gxbb-gpio-intc";
+ reg = <0x0 0x9880 0x0 0x10>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+};
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Jerome Brunet <jbrunet@baylibre.com>
To: Carlo Caione <carlo@caione.org>,
Kevin Hilman <khilman@baylibre.com>,
Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
Marc Zyngier <marc.zyngier@arm.com>,
Rob Herring <robh+dt@kernel.org>
Cc: Jerome Brunet <jbrunet@baylibre.com>,
linux-amlogic@lists.infradead.org,
linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
Linus Walleij <linus.walleij@linaro.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will.deacon@arm.com>,
Russell King <linux@armlinux.org.uk>
Subject: [PATCH 2/9] dt-bindings: interrupt-controller: add DT binding for meson GPIO interrupt controller
Date: Wed, 19 Oct 2016 12:08:22 +0200 [thread overview]
Message-ID: <1476871709-8359-3-git-send-email-jbrunet@baylibre.com> (raw)
In-Reply-To: <1476871709-8359-1-git-send-email-jbrunet@baylibre.com>
This commit adds the device tree bindings description for Amlogic's GPIO
interrupt controller available on the meson8, meson8b and gxbb SoC families
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
Rob, I did not include the Ack you gave for the RFC as bindings have slightly
changed. Only the interrupt property has be removed following a discussion I
had with Marc.
.../amlogic,meson-gpio-intc.txt | 31 ++++++++++++++++++++++
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
new file mode 100644
index 000000000000..2464d9a0865d
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
@@ -0,0 +1,31 @@
+Amlogic meson GPIO interrupt controller
+
+Meson SoCs contains an interrupt controller which is able watch the SoC pads
+and generate an interrupt on edges or level. The controller is essentially a
+256 pads to 8 GIC interrupt multiplexer, with a filter block to select edge
+or level and polarity. We don’t expose all 256 mux inputs because the
+documentation shows that upper part is not mapped to any pad. The actual number
+of interrupt exposed depends on the SoC.
+
+Required properties:
+
+- compatible : should be either
+ "amlogic,meson8-gpio-intc” for meson8 SoCs (AML7826MX) or
+ “amlogic,meson8b-gpio-intc” for meson8b SoCs (S805) or
+ “amlogic,meson-gxbb-gpio-intc” for GXBB SoCs (S905)
+- interrupt-parent : a phandle to the GIC the interrupts are routed to.
+ Usually this is provided at the root level of the device tree as it is
+ common to most of the SoC
+- reg : Specifies base physical address and size of the registers.
+- interrupt-controller : Identifies the node as an interrupt controller.
+- #interrupt-cells : Specifies the number of cells needed to encode an
+ interrupt source. The value must be 2.
+
+Example:
+
+gpio_interrupt: interrupt-controller@9880 {
+ compatible = "amlogic,meson-gxbb-gpio-intc";
+ reg = <0x0 0x9880 0x0 0x10>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+};
--
2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: jbrunet@baylibre.com (Jerome Brunet)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/9] dt-bindings: interrupt-controller: add DT binding for meson GPIO interrupt controller
Date: Wed, 19 Oct 2016 12:08:22 +0200 [thread overview]
Message-ID: <1476871709-8359-3-git-send-email-jbrunet@baylibre.com> (raw)
In-Reply-To: <1476871709-8359-1-git-send-email-jbrunet@baylibre.com>
This commit adds the device tree bindings description for Amlogic's GPIO
interrupt controller available on the meson8, meson8b and gxbb SoC families
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
Rob, I did not include the Ack you gave for the RFC as bindings have slightly
changed. Only the interrupt property has be removed following a discussion I
had with Marc.
.../amlogic,meson-gpio-intc.txt | 31 ++++++++++++++++++++++
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
new file mode 100644
index 000000000000..2464d9a0865d
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
@@ -0,0 +1,31 @@
+Amlogic meson GPIO interrupt controller
+
+Meson SoCs contains an interrupt controller which is able watch the SoC pads
+and generate an interrupt on edges or level. The controller is essentially a
+256 pads to 8 GIC interrupt multiplexer, with a filter block to select edge
+or level and polarity. We don?t expose all 256 mux inputs because the
+documentation shows that upper part is not mapped to any pad. The actual number
+of interrupt exposed depends on the SoC.
+
+Required properties:
+
+- compatible : should be either
+ "amlogic,meson8-gpio-intc? for meson8 SoCs (AML7826MX) or
+ ?amlogic,meson8b-gpio-intc? for meson8b SoCs (S805) or
+ ?amlogic,meson-gxbb-gpio-intc? for GXBB SoCs (S905)
+- interrupt-parent : a phandle to the GIC the interrupts are routed to.
+ Usually this is provided at the root level of the device tree as it is
+ common to most of the SoC
+- reg : Specifies base physical address and size of the registers.
+- interrupt-controller : Identifies the node as an interrupt controller.
+- #interrupt-cells : Specifies the number of cells needed to encode an
+ interrupt source. The value must be 2.
+
+Example:
+
+gpio_interrupt: interrupt-controller at 9880 {
+ compatible = "amlogic,meson-gxbb-gpio-intc";
+ reg = <0x0 0x9880 0x0 0x10>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+};
--
2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: jbrunet@baylibre.com (Jerome Brunet)
To: linus-amlogic@lists.infradead.org
Subject: [PATCH 2/9] dt-bindings: interrupt-controller: add DT binding for meson GPIO interrupt controller
Date: Wed, 19 Oct 2016 12:08:22 +0200 [thread overview]
Message-ID: <1476871709-8359-3-git-send-email-jbrunet@baylibre.com> (raw)
In-Reply-To: <1476871709-8359-1-git-send-email-jbrunet@baylibre.com>
This commit adds the device tree bindings description for Amlogic's GPIO
interrupt controller available on the meson8, meson8b and gxbb SoC families
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
Rob, I did not include the Ack you gave for the RFC as bindings have slightly
changed. Only the interrupt property has be removed following a discussion I
had with Marc.
.../amlogic,meson-gpio-intc.txt | 31 ++++++++++++++++++++++
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
new file mode 100644
index 000000000000..2464d9a0865d
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
@@ -0,0 +1,31 @@
+Amlogic meson GPIO interrupt controller
+
+Meson SoCs contains an interrupt controller which is able watch the SoC pads
+and generate an interrupt on edges or level. The controller is essentially a
+256 pads to 8 GIC interrupt multiplexer, with a filter block to select edge
+or level and polarity. We don?t expose all 256 mux inputs because the
+documentation shows that upper part is not mapped to any pad. The actual number
+of interrupt exposed depends on the SoC.
+
+Required properties:
+
+- compatible : should be either
+ "amlogic,meson8-gpio-intc? for meson8 SoCs (AML7826MX) or
+ ?amlogic,meson8b-gpio-intc? for meson8b SoCs (S805) or
+ ?amlogic,meson-gxbb-gpio-intc? for GXBB SoCs (S905)
+- interrupt-parent : a phandle to the GIC the interrupts are routed to.
+ Usually this is provided at the root level of the device tree as it is
+ common to most of the SoC
+- reg : Specifies base physical address and size of the registers.
+- interrupt-controller : Identifies the node as an interrupt controller.
+- #interrupt-cells : Specifies the number of cells needed to encode an
+ interrupt source. The value must be 2.
+
+Example:
+
+gpio_interrupt: interrupt-controller at 9880 {
+ compatible = "amlogic,meson-gxbb-gpio-intc";
+ reg = <0x0 0x9880 0x0 0x10>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+};
--
2.7.4
next prev parent reply other threads:[~2016-10-19 10:08 UTC|newest]
Thread overview: 120+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-19 10:08 [PATCH 0/9] irqchip: meson: add support for the gpio interrupt controller Jerome Brunet
2016-10-19 10:08 ` Jerome Brunet
2016-10-19 10:08 ` Jerome Brunet
2016-10-19 10:08 ` Jerome Brunet
2016-10-19 10:08 ` [PATCH 1/9] irqchip: meson: add support for " Jerome Brunet
2016-10-19 10:08 ` Jerome Brunet
2016-10-19 10:08 ` Jerome Brunet
2016-10-19 10:08 ` Jerome Brunet
2016-10-19 10:08 ` Jerome Brunet [this message]
2016-10-19 10:08 ` [PATCH 2/9] dt-bindings: interrupt-controller: add DT binding for meson GPIO " Jerome Brunet
2016-10-19 10:08 ` Jerome Brunet
2016-10-19 10:08 ` Jerome Brunet
2016-10-19 10:08 ` [PATCH 3/9] pinctrl: meson: update pinctrl data with gpio irq data Jerome Brunet
2016-10-19 10:08 ` Jerome Brunet
2016-10-19 10:08 ` Jerome Brunet
2016-10-19 10:08 ` Jerome Brunet
2016-10-19 10:08 ` [PATCH 4/9] pinctrl: meson: allow gpio to request irq Jerome Brunet
2016-10-19 10:08 ` Jerome Brunet
2016-10-19 10:08 ` Jerome Brunet
2016-10-19 10:08 ` Jerome Brunet
2016-10-20 19:21 ` Linus Walleij
2016-10-20 19:21 ` Linus Walleij
2016-10-20 19:21 ` Linus Walleij
2016-10-20 19:21 ` Linus Walleij
2016-10-21 9:06 ` Jerome Brunet
2016-10-21 9:06 ` Jerome Brunet
2016-10-21 9:06 ` Jerome Brunet
2016-10-21 9:06 ` Jerome Brunet
2016-10-25 9:14 ` Linus Walleij
2016-10-25 9:14 ` Linus Walleij
2016-10-25 9:14 ` Linus Walleij
2016-10-25 9:14 ` Linus Walleij
2016-10-25 10:38 ` Marc Zyngier
2016-10-25 10:38 ` Marc Zyngier
2016-10-25 10:38 ` Marc Zyngier
2016-10-25 10:38 ` Marc Zyngier
2016-10-25 13:08 ` Jerome Brunet
2016-10-25 13:08 ` Jerome Brunet
2016-10-25 13:08 ` Jerome Brunet
2016-10-25 13:08 ` Jerome Brunet
[not found] ` <1477400900.2482.51.camel-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
2016-10-25 13:38 ` Marc Zyngier
2016-10-25 13:38 ` Marc Zyngier
2016-10-25 13:38 ` Marc Zyngier
2016-10-25 13:38 ` Marc Zyngier
2016-10-25 14:22 ` Jerome Brunet
2016-10-25 14:22 ` Jerome Brunet
2016-10-25 14:22 ` Jerome Brunet
2016-10-25 14:22 ` Jerome Brunet
[not found] ` <1477405332.2482.87.camel-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
2016-10-25 14:47 ` Marc Zyngier
2016-10-25 14:47 ` Marc Zyngier
2016-10-25 14:47 ` Marc Zyngier
2016-10-25 14:47 ` Marc Zyngier
2016-10-25 15:31 ` Jerome Brunet
2016-10-25 15:31 ` Jerome Brunet
2016-10-25 15:31 ` Jerome Brunet
2016-10-25 15:31 ` Jerome Brunet
2016-10-25 18:20 ` Linus Walleij
2016-10-25 18:20 ` Linus Walleij
2016-10-25 18:20 ` Linus Walleij
2016-10-25 18:20 ` Linus Walleij
[not found] ` <CACRpkdbGo4BJOdzkgBrE9jT-rKodd4zssCnOtOuGS+OqV-Uc6Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-10-26 14:22 ` Jerome Brunet
2016-10-26 14:22 ` Jerome Brunet
2016-10-26 14:22 ` Jerome Brunet
2016-10-26 14:22 ` Jerome Brunet
[not found] ` <1477491766.2482.159.camel-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
2016-10-26 14:32 ` Linus Walleij
2016-10-26 14:32 ` Linus Walleij
2016-10-26 14:32 ` Linus Walleij
2016-10-26 14:32 ` Linus Walleij
2016-10-26 15:50 ` Kevin Hilman
2016-10-26 15:50 ` Kevin Hilman
2016-10-26 15:50 ` Kevin Hilman
2016-10-26 15:50 ` Kevin Hilman
2016-11-04 14:40 ` Linus Walleij
2016-11-04 14:40 ` Linus Walleij
2016-11-04 14:40 ` Linus Walleij
2016-11-04 14:40 ` Linus Walleij
2016-10-25 18:10 ` Linus Walleij
2016-10-25 18:10 ` Linus Walleij
2016-10-25 18:10 ` Linus Walleij
2016-10-25 18:10 ` Linus Walleij
2016-10-26 14:23 ` Jerome Brunet
2016-10-26 14:23 ` Jerome Brunet
2016-10-26 14:23 ` Jerome Brunet
2016-10-26 14:23 ` Jerome Brunet
[not found] ` <1477491816.2482.160.camel-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
2016-10-26 14:44 ` Linus Walleij
2016-10-26 14:44 ` Linus Walleij
2016-10-26 14:44 ` Linus Walleij
2016-10-26 14:44 ` Linus Walleij
2016-10-27 10:42 ` Jerome Brunet
2016-10-27 10:42 ` Jerome Brunet
2016-10-27 10:42 ` Jerome Brunet
2016-10-27 10:42 ` Jerome Brunet
2016-11-04 15:03 ` Linus Walleij
2016-11-04 15:03 ` Linus Walleij
2016-11-04 15:03 ` Linus Walleij
2016-11-04 15:03 ` Linus Walleij
[not found] ` <CACRpkdYUVXny57AC9rKX3VRAyooEk_2XLvqe9jOuT3rOaE75rg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-10-25 10:39 ` Thomas Gleixner
2016-10-25 10:39 ` Thomas Gleixner
2016-10-25 10:39 ` Thomas Gleixner
2016-10-25 10:39 ` Thomas Gleixner
2016-10-19 10:08 ` [PATCH 5/9] dt-bindings: pinctrl: meson: update gpio dt-bindings Jerome Brunet
2016-10-19 10:08 ` Jerome Brunet
2016-10-19 10:08 ` Jerome Brunet
2016-10-19 10:08 ` Jerome Brunet
2016-10-19 10:08 ` [PATCH 6/9] ARM64: meson: enable MESON_IRQ_GPIO in Kconfig Jerome Brunet
2016-10-19 10:08 ` Jerome Brunet
2016-10-19 10:08 ` Jerome Brunet
2016-10-19 10:08 ` Jerome Brunet
2016-10-19 10:08 ` [PATCH 7/9] ARM: meson: enable MESON_IRQ_GPIO in Kconfig for meson8 Jerome Brunet
2016-10-19 10:08 ` Jerome Brunet
2016-10-19 10:08 ` Jerome Brunet
2016-10-19 10:08 ` Jerome Brunet
2016-10-19 10:08 ` [PATCH 8/9] ARM64: dts: amlogic: enable gpio interrupt controller on gxbb Jerome Brunet
2016-10-19 10:08 ` Jerome Brunet
2016-10-19 10:08 ` Jerome Brunet
2016-10-19 10:08 ` Jerome Brunet
2016-10-19 10:08 ` [PATCH 9/9] ARM: dts: amlogic: enable gpio interrupt controller on meson8 Jerome Brunet
2016-10-19 10:08 ` Jerome Brunet
2016-10-19 10:08 ` Jerome Brunet
2016-10-19 10:08 ` Jerome Brunet
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1476871709-8359-3-git-send-email-jbrunet@baylibre.com \
--to=jbrunet@baylibre.com \
--cc=carlo@caione.org \
--cc=catalin.marinas@arm.com \
--cc=devicetree@vger.kernel.org \
--cc=jason@lakedaemon.net \
--cc=khilman@baylibre.com \
--cc=linus.walleij@linaro.org \
--cc=linux-amlogic@lists.infradead.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-gpio@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux@armlinux.org.uk \
--cc=marc.zyngier@arm.com \
--cc=robh+dt@kernel.org \
--cc=tglx@linutronix.de \
--cc=will.deacon@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.