From: Daniel Lezcano <daniel.lezcano@linaro.org> To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Marc Zyngier <marc.zyngier@arm.com>, Mark Rutland <mark.rutland@arm.com>, Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will.deacon@arm.com>, Suzuki K Poulose <suzuki.poulose@arm.com>, Andre Przywara <andre.przywara@arm.com>, Ingo Molnar <mingo@kernel.org>, linux-arm-kernel@lists.infradead.org (moderated list:ARM64 PORT (AARCH64 ARCHITECTURE)) Subject: [PATCH 02/29] arm64: Add CNTVCT_EL0 trap handler Date: Sun, 16 Apr 2017 22:26:52 +0200 [thread overview] Message-ID: <1492374441-23336-2-git-send-email-daniel.lezcano@linaro.org> (raw) In-Reply-To: <1492374441-23336-1-git-send-email-daniel.lezcano@linaro.org> From: Marc Zyngier <marc.zyngier@arm.com> Since people seem to make a point in breaking the userspace visible counter, we have no choice but to trap the access. Add the required handler. Acked-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> --- arch/arm64/include/asm/esr.h | 2 ++ arch/arm64/kernel/traps.c | 14 ++++++++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h index d14c478..ad42e79 100644 --- a/arch/arm64/include/asm/esr.h +++ b/arch/arm64/include/asm/esr.h @@ -175,6 +175,8 @@ #define ESR_ELx_SYS64_ISS_SYS_CTR_READ (ESR_ELx_SYS64_ISS_SYS_CTR | \ ESR_ELx_SYS64_ISS_DIR_READ) +#define ESR_ELx_SYS64_ISS_SYS_CNTVCT (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \ + ESR_ELx_SYS64_ISS_DIR_READ) #ifndef __ASSEMBLY__ #include <asm/types.h> diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c index e52be6a..1de444e 100644 --- a/arch/arm64/kernel/traps.c +++ b/arch/arm64/kernel/traps.c @@ -505,6 +505,14 @@ static void ctr_read_handler(unsigned int esr, struct pt_regs *regs) regs->pc += 4; } +static void cntvct_read_handler(unsigned int esr, struct pt_regs *regs) +{ + int rt = (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT; + + pt_regs_write_reg(regs, rt, arch_counter_get_cntvct()); + regs->pc += 4; +} + struct sys64_hook { unsigned int esr_mask; unsigned int esr_val; @@ -523,6 +531,12 @@ static struct sys64_hook sys64_hooks[] = { .esr_val = ESR_ELx_SYS64_ISS_SYS_CTR_READ, .handler = ctr_read_handler, }, + { + /* Trap read access to CNTVCT_EL0 */ + .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK, + .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTVCT, + .handler = cntvct_read_handler, + }, {}, }; -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: daniel.lezcano@linaro.org (Daniel Lezcano) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 02/29] arm64: Add CNTVCT_EL0 trap handler Date: Sun, 16 Apr 2017 22:26:52 +0200 [thread overview] Message-ID: <1492374441-23336-2-git-send-email-daniel.lezcano@linaro.org> (raw) In-Reply-To: <1492374441-23336-1-git-send-email-daniel.lezcano@linaro.org> From: Marc Zyngier <marc.zyngier@arm.com> Since people seem to make a point in breaking the userspace visible counter, we have no choice but to trap the access. Add the required handler. Acked-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> --- arch/arm64/include/asm/esr.h | 2 ++ arch/arm64/kernel/traps.c | 14 ++++++++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h index d14c478..ad42e79 100644 --- a/arch/arm64/include/asm/esr.h +++ b/arch/arm64/include/asm/esr.h @@ -175,6 +175,8 @@ #define ESR_ELx_SYS64_ISS_SYS_CTR_READ (ESR_ELx_SYS64_ISS_SYS_CTR | \ ESR_ELx_SYS64_ISS_DIR_READ) +#define ESR_ELx_SYS64_ISS_SYS_CNTVCT (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \ + ESR_ELx_SYS64_ISS_DIR_READ) #ifndef __ASSEMBLY__ #include <asm/types.h> diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c index e52be6a..1de444e 100644 --- a/arch/arm64/kernel/traps.c +++ b/arch/arm64/kernel/traps.c @@ -505,6 +505,14 @@ static void ctr_read_handler(unsigned int esr, struct pt_regs *regs) regs->pc += 4; } +static void cntvct_read_handler(unsigned int esr, struct pt_regs *regs) +{ + int rt = (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT; + + pt_regs_write_reg(regs, rt, arch_counter_get_cntvct()); + regs->pc += 4; +} + struct sys64_hook { unsigned int esr_mask; unsigned int esr_val; @@ -523,6 +531,12 @@ static struct sys64_hook sys64_hooks[] = { .esr_val = ESR_ELx_SYS64_ISS_SYS_CTR_READ, .handler = ctr_read_handler, }, + { + /* Trap read access to CNTVCT_EL0 */ + .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK, + .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTVCT, + .handler = cntvct_read_handler, + }, {}, }; -- 2.7.4
next prev parent reply other threads:[~2017-04-16 20:33 UTC|newest] Thread overview: 71+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-04-16 20:25 [GIT PULL] timers changes for 4.12 Daniel Lezcano 2017-04-16 20:26 ` [PATCH 01/29] arm64: Allow checking of a CPU-local erratum Daniel Lezcano 2017-04-16 20:26 ` Daniel Lezcano 2017-04-16 20:26 ` Daniel Lezcano [this message] 2017-04-16 20:26 ` [PATCH 02/29] arm64: Add CNTVCT_EL0 trap handler Daniel Lezcano 2017-04-16 20:26 ` [PATCH 03/29] arm64: Define Cortex-A73 MIDR Daniel Lezcano 2017-04-16 20:26 ` Daniel Lezcano 2017-04-16 20:26 ` [PATCH 04/29] arm64: cpu_errata: Allow an erratum to be match for all revisions of a core Daniel Lezcano 2017-04-16 20:26 ` Daniel Lezcano 2017-04-16 20:26 ` [PATCH 05/29] arm64: cpu_errata: Add capability to advertise Cortex-A73 erratum 858921 Daniel Lezcano 2017-04-16 20:26 ` Daniel Lezcano 2017-04-16 20:26 ` [PATCH 06/29] arm64: arch_timer: Add infrastructure for multiple erratum detection methods Daniel Lezcano 2017-04-16 20:26 ` Daniel Lezcano 2017-04-16 20:26 ` [PATCH 07/29] arm64: arch_timer: Add erratum handler for CPU-specific capability Daniel Lezcano 2017-04-16 20:26 ` Daniel Lezcano 2017-04-16 20:26 ` [PATCH 08/29] arm64: arch_timer: Move arch_timer_reg_read/write around Daniel Lezcano 2017-04-16 20:26 ` Daniel Lezcano 2017-04-16 20:26 ` [PATCH 09/29] arm64: arch_timer: Get rid of erratum_workaround_set_sne Daniel Lezcano 2017-04-16 20:26 ` Daniel Lezcano 2017-04-16 20:27 ` [PATCH 10/29] arm64: arch_timer: Rework the set_next_event workarounds Daniel Lezcano 2017-04-16 20:27 ` Daniel Lezcano 2017-04-16 20:27 ` [PATCH 11/29] arm64: arch_timer: Make workaround methods optional Daniel Lezcano 2017-04-16 20:27 ` Daniel Lezcano 2017-04-16 20:27 ` [PATCH 12/29] arm64: arch_timer: Allows a CPU-specific erratum to only affect a subset of CPUs Daniel Lezcano 2017-04-16 20:27 ` Daniel Lezcano 2017-04-16 20:27 ` [PATCH 13/29] arm64: arch_timer: Move clocksource_counter and co around Daniel Lezcano 2017-04-16 20:27 ` Daniel Lezcano 2017-04-16 20:27 ` [PATCH 14/29] arm64: arch_timer: Save cntkctl_el1 as a per-cpu variable Daniel Lezcano 2017-04-16 20:27 ` Daniel Lezcano 2017-04-16 20:27 ` [PATCH 15/29] arm64: arch_timer: Enable CNTVCT_EL0 trap if workaround is enabled Daniel Lezcano 2017-04-16 20:27 ` Daniel Lezcano 2017-04-16 20:27 ` [PATCH 16/29] arm64: arch_timer: Workaround for Cortex-A73 erratum 858921 Daniel Lezcano 2017-04-16 20:27 ` Daniel Lezcano 2017-04-16 20:27 ` [PATCH 17/29] arm64: arch_timer: Allow erratum matching with ACPI OEM information Daniel Lezcano 2017-04-16 20:27 ` Daniel Lezcano 2017-04-16 20:27 ` [PATCH 18/29] arm64: arch_timer: Add HISILICON_ERRATUM_161010101 ACPI matching data Daniel Lezcano 2017-04-16 20:27 ` Daniel Lezcano 2017-04-16 20:27 ` [PATCH 19/29] clocksource/drivers/orion: Read clock rate once Daniel Lezcano 2017-04-16 20:27 ` [PATCH 20/29] clocksource/drivers/orion: Add delay_timer implementation Daniel Lezcano 2017-04-16 20:27 ` [PATCH 21/29] clocksource: Add missing line break to error messages Daniel Lezcano 2017-04-16 20:27 ` Daniel Lezcano 2017-04-16 20:27 ` Daniel Lezcano 2017-04-16 20:27 ` Daniel Lezcano 2017-04-16 20:27 ` Daniel Lezcano [not found] ` <1492374441-23336-21-git-send-email-daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> 2017-04-24 7:45 ` Uwe Kleine-König 2017-04-24 7:45 ` Uwe Kleine-König 2017-04-24 7:45 ` Uwe Kleine-König 2017-04-24 7:45 ` Uwe Kleine-König 2017-04-24 7:45 ` Uwe Kleine-König 2017-04-16 20:27 ` [PATCH 22/29] dt-bindings: Clarify compatible property for rockchip timers Daniel Lezcano 2017-04-16 20:27 ` Daniel Lezcano 2017-04-16 20:27 ` Daniel Lezcano 2017-04-20 14:12 ` Rob Herring 2017-04-20 14:12 ` Rob Herring 2017-04-20 14:12 ` Rob Herring 2017-04-16 20:27 ` [PATCH 23/29] ARM: dts: rockchip: Update compatible property for rk322x timer Daniel Lezcano 2017-04-16 20:27 ` Daniel Lezcano 2017-04-16 20:27 ` Daniel Lezcano 2017-04-16 20:27 ` [PATCH 24/29] clocksource/drivers/rockchip_timer: Implement clocksource timer Daniel Lezcano 2017-04-16 20:27 ` Daniel Lezcano 2017-04-16 20:27 ` Daniel Lezcano 2017-04-16 20:27 ` [PATCH 25/29] ARM: dts: rockchip: Add timer entries to rk3188 SoC Daniel Lezcano 2017-04-16 20:27 ` Daniel Lezcano 2017-04-16 20:27 ` Daniel Lezcano 2017-04-16 20:27 ` [PATCH 26/29] ARM: dts: rockchip: disable arm-global-timer for rk3188 Daniel Lezcano 2017-04-16 20:27 ` Daniel Lezcano 2017-04-16 20:27 ` Daniel Lezcano 2017-04-16 20:27 ` [PATCH 27/29] clocksource: Augment bindings for Faraday timer Daniel Lezcano 2017-04-16 20:27 ` Daniel Lezcano 2017-04-16 20:27 ` [PATCH 28/29] clocksource/drivers/gemini: Rename Gemini timer to Faraday Daniel Lezcano 2017-04-16 20:27 ` [PATCH 29/29] clocksource/drivers/fttmr010: Refactor to handle clock Daniel Lezcano
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