From: Ludovic Barre <ludovic.Barre@st.com> To: Thomas Gleixner <tglx@linutronix.de>, Jason Cooper <jason@lakedaemon.net>, Marc Zyngier <marc.zyngier@arm.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>, Alexandre Torgue <alexandre.torgue@st.com>, <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org> Subject: [PATCH 5/8] irqchip: stm32: fix initial values Date: Fri, 7 Jul 2017 09:26:28 +0200 [thread overview] Message-ID: <1499412391-25480-6-git-send-email-ludovic.Barre@st.com> (raw) In-Reply-To: <1499412391-25480-1-git-send-email-ludovic.Barre@st.com> From: Ludovic Barre <ludovic.barre@st.com> -after cold boot, imr default value depend of hw configuration -after hot reboot the registers must be cleared to avoid residue Signed-off-by: Ludovic Barre <ludovic.barre@st.com> --- drivers/irqchip/irq-stm32-exti.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c index 69ae09d..3c7077d 100644 --- a/drivers/irqchip/irq-stm32-exti.c +++ b/drivers/irqchip/irq-stm32-exti.c @@ -246,7 +246,16 @@ static int __init stm32_exti_init(struct stm32_exti_bank **stm32_exti_banks, irqs_mask = readl_relaxed(base + stm32_bank->rtsr_ofst); stm32_bank->irqs_mask = irqs_mask; nr_exti = fls(readl_relaxed(base + stm32_bank->rtsr_ofst)); + + /* + * This IP has no reset, so after hot reboot we should + * clear registers to avoid residue + */ + writel_relaxed(0, base + stm32_bank->imr_ofst); + writel_relaxed(0, base + stm32_bank->emr_ofst); writel_relaxed(0, base + stm32_bank->rtsr_ofst); + writel_relaxed(0, base + stm32_bank->ftsr_ofst); + writel_relaxed(~0UL, base + stm32_bank->pr_ofst); pr_info("%s: bank%d, External IRQs available:%#x\n", node->full_name, i, irqs_mask); -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: ludovic.Barre@st.com (Ludovic Barre) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 5/8] irqchip: stm32: fix initial values Date: Fri, 7 Jul 2017 09:26:28 +0200 [thread overview] Message-ID: <1499412391-25480-6-git-send-email-ludovic.Barre@st.com> (raw) In-Reply-To: <1499412391-25480-1-git-send-email-ludovic.Barre@st.com> From: Ludovic Barre <ludovic.barre@st.com> -after cold boot, imr default value depend of hw configuration -after hot reboot the registers must be cleared to avoid residue Signed-off-by: Ludovic Barre <ludovic.barre@st.com> --- drivers/irqchip/irq-stm32-exti.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c index 69ae09d..3c7077d 100644 --- a/drivers/irqchip/irq-stm32-exti.c +++ b/drivers/irqchip/irq-stm32-exti.c @@ -246,7 +246,16 @@ static int __init stm32_exti_init(struct stm32_exti_bank **stm32_exti_banks, irqs_mask = readl_relaxed(base + stm32_bank->rtsr_ofst); stm32_bank->irqs_mask = irqs_mask; nr_exti = fls(readl_relaxed(base + stm32_bank->rtsr_ofst)); + + /* + * This IP has no reset, so after hot reboot we should + * clear registers to avoid residue + */ + writel_relaxed(0, base + stm32_bank->imr_ofst); + writel_relaxed(0, base + stm32_bank->emr_ofst); writel_relaxed(0, base + stm32_bank->rtsr_ofst); + writel_relaxed(0, base + stm32_bank->ftsr_ofst); + writel_relaxed(~0UL, base + stm32_bank->pr_ofst); pr_info("%s: bank%d, External IRQs available:%#x\n", node->full_name, i, irqs_mask); -- 2.7.4
next prev parent reply other threads:[~2017-07-07 7:28 UTC|newest] Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-07-07 7:26 [PATCH 0/8] irqchip: stm32: add stm32h7 support Ludovic Barre 2017-07-07 7:26 ` Ludovic Barre 2017-07-07 7:26 ` [PATCH 1/8] irqchip: stm32: select GENERIC_IRQ_CHIP Ludovic Barre 2017-07-07 7:26 ` Ludovic Barre 2017-07-07 7:26 ` [PATCH 2/8] irqchip: stm32: add multi-bank management Ludovic Barre 2017-07-07 7:26 ` Ludovic Barre 2017-08-07 13:21 ` Marc Zyngier 2017-08-07 13:21 ` Marc Zyngier 2017-08-08 9:28 ` Ludovic BARRE 2017-08-08 9:28 ` Ludovic BARRE 2017-07-07 7:26 ` [PATCH 3/8] dt-bindings: interrupt-controllers: add compatible string for stm32h7 Ludovic Barre 2017-07-07 7:26 ` Ludovic Barre 2017-07-07 7:26 ` [PATCH 4/8] irqchip: stm32: add stm32h7 support Ludovic Barre 2017-07-07 7:26 ` Ludovic Barre 2017-07-07 7:26 ` Ludovic Barre [this message] 2017-07-07 7:26 ` [PATCH 5/8] irqchip: stm32: fix initial values Ludovic Barre 2017-07-07 7:26 ` [PATCH 6/8] irqchip: stm32: move the wakeup on interrupt mask Ludovic Barre 2017-07-07 7:26 ` Ludovic Barre 2017-07-07 7:26 ` [PATCH 7/8] ARM: dts: stm32: add exti support for stm32h743 Ludovic Barre 2017-07-07 7:26 ` Ludovic Barre 2017-07-07 7:26 ` [PATCH 8/8] ARM: dts: stm32: add support of exti on stm32h743 pinctrl Ludovic Barre 2017-07-07 7:26 ` Ludovic Barre 2017-07-07 8:16 ` Alexandre Torgue 2017-07-07 8:16 ` Alexandre Torgue
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=1499412391-25480-6-git-send-email-ludovic.Barre@st.com \ --to=ludovic.barre@st.com \ --cc=alexandre.torgue@st.com \ --cc=jason@lakedaemon.net \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-kernel@vger.kernel.org \ --cc=marc.zyngier@arm.com \ --cc=mcoquelin.stm32@gmail.com \ --cc=tglx@linutronix.de \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.