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From: Jerome Brunet <jbrunet@baylibre.com>
To: Yixun Lan <yixun.lan@amlogic.com>,
	Neil Armstrong <narmstrong@baylibre.com>,
	Kevin Hilman <khilman@baylibre.com>,
	Carlo Caione <carlo@caione.org>
Cc: Rob Herring <robh@kernel.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@codeaurora.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Qiufang Dai <qiufang.dai@amlogic.com>,
	linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v2 7/7] ARM64: dts: meson-axg: add an 32K alt aoclk
Date: Tue, 27 Mar 2018 11:00:49 +0200	[thread overview]
Message-ID: <1522141249.2632.25.camel@baylibre.com> (raw)
In-Reply-To: <20180323143816.200573-8-yixun.lan@amlogic.com>

On Fri, 2018-03-23 at 22:38 +0800, Yixun Lan wrote:
> The ao_clk81 in AO domain have two clock source,
> one from a 32K alt crystal we name it as ao_alt_clk,
> another is the clk81 signal from EE domain.
> 
> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
> ---
>  arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> index b3d394f5d95a..48584d5a329b 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> @@ -109,6 +109,13 @@
>  		#clock-cells = <0>;
>  	};
>  
> +	ao_alt_xtal: ao_alt_xtal-clk {
> +		compatible = "fixed-clock";
> +		clock-frequency = <32000000>;
> +		clock-output-names = "ao_alt_xtal";
> +		#clock-cells = <0>;
> +	};

In DT, we seem to be using 'ao' and 'AO' to designate the Always On domain.
Maybe we should be try be consistent about this.

Anyway, this patch looks good but does not need to be part of the clkc_ao
series, it could go in independently.

Acked-by: Jerome Brunet <jbrunet@baylibre.com>

> +
>  	soc {
>  		compatible = "simple-bus";
>  		#address-cells = <2>;

WARNING: multiple messages have this Message-ID (diff)
From: jbrunet@baylibre.com (Jerome Brunet)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 7/7] ARM64: dts: meson-axg: add an 32K alt aoclk
Date: Tue, 27 Mar 2018 11:00:49 +0200	[thread overview]
Message-ID: <1522141249.2632.25.camel@baylibre.com> (raw)
In-Reply-To: <20180323143816.200573-8-yixun.lan@amlogic.com>

On Fri, 2018-03-23 at 22:38 +0800, Yixun Lan wrote:
> The ao_clk81 in AO domain have two clock source,
> one from a 32K alt crystal we name it as ao_alt_clk,
> another is the clk81 signal from EE domain.
> 
> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
> ---
>  arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> index b3d394f5d95a..48584d5a329b 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> @@ -109,6 +109,13 @@
>  		#clock-cells = <0>;
>  	};
>  
> +	ao_alt_xtal: ao_alt_xtal-clk {
> +		compatible = "fixed-clock";
> +		clock-frequency = <32000000>;
> +		clock-output-names = "ao_alt_xtal";
> +		#clock-cells = <0>;
> +	};

In DT, we seem to be using 'ao' and 'AO' to designate the Always On domain.
Maybe we should be try be consistent about this.

Anyway, this patch looks good but does not need to be part of the clkc_ao
series, it could go in independently.

Acked-by: Jerome Brunet <jbrunet@baylibre.com>

> +
>  	soc {
>  		compatible = "simple-bus";
>  		#address-cells = <2>;

WARNING: multiple messages have this Message-ID (diff)
From: jbrunet@baylibre.com (Jerome Brunet)
To: linus-amlogic@lists.infradead.org
Subject: [PATCH v2 7/7] ARM64: dts: meson-axg: add an 32K alt aoclk
Date: Tue, 27 Mar 2018 11:00:49 +0200	[thread overview]
Message-ID: <1522141249.2632.25.camel@baylibre.com> (raw)
In-Reply-To: <20180323143816.200573-8-yixun.lan@amlogic.com>

On Fri, 2018-03-23 at 22:38 +0800, Yixun Lan wrote:
> The ao_clk81 in AO domain have two clock source,
> one from a 32K alt crystal we name it as ao_alt_clk,
> another is the clk81 signal from EE domain.
> 
> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
> ---
>  arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> index b3d394f5d95a..48584d5a329b 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> @@ -109,6 +109,13 @@
>  		#clock-cells = <0>;
>  	};
>  
> +	ao_alt_xtal: ao_alt_xtal-clk {
> +		compatible = "fixed-clock";
> +		clock-frequency = <32000000>;
> +		clock-output-names = "ao_alt_xtal";
> +		#clock-cells = <0>;
> +	};

In DT, we seem to be using 'ao' and 'AO' to designate the Always On domain.
Maybe we should be try be consistent about this.

Anyway, this patch looks good but does not need to be part of the clkc_ao
series, it could go in independently.

Acked-by: Jerome Brunet <jbrunet@baylibre.com>

> +
>  	soc {
>  		compatible = "simple-bus";
>  		#address-cells = <2>;

  reply	other threads:[~2018-03-27  9:00 UTC|newest]

Thread overview: 47+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-23 14:38 [PATCH v2 0/7] clk: meson-axg: Add AO Cloclk and Reset driver Yixun Lan
2018-03-23 14:38 ` Yixun Lan
2018-03-23 14:38 ` Yixun Lan
2018-03-23 14:38 ` Yixun Lan
2018-03-23 14:38 ` [PATCH v2 1/7] clk: meson: drop meson_aoclk_gate_regmap_ops Yixun Lan
2018-03-23 14:38   ` Yixun Lan
2018-03-23 14:38   ` Yixun Lan
2018-03-27  8:40   ` Jerome Brunet
2018-03-27  8:40     ` Jerome Brunet
2018-03-27  8:40     ` Jerome Brunet
2018-03-27  8:40     ` Jerome Brunet
2018-03-23 14:38 ` [PATCH v2 2/7] clk: meson: aoclk: refactor common code into dedicated file Yixun Lan
2018-03-23 14:38   ` Yixun Lan
2018-03-23 14:38   ` Yixun Lan
2018-03-27  8:30   ` Jerome Brunet
2018-03-27  8:30     ` Jerome Brunet
2018-03-27  8:30     ` Jerome Brunet
2018-03-27  8:30     ` Jerome Brunet
2018-03-23 14:38 ` [PATCH v2 3/7] dt-bindings: clock: axg-aoclkc: New binding for Meson-AXG SoC Yixun Lan
2018-03-23 14:38   ` Yixun Lan
2018-03-23 14:38   ` Yixun Lan
2018-03-23 14:38   ` Yixun Lan
2018-03-26 22:25   ` Rob Herring
2018-03-26 22:25     ` Rob Herring
2018-03-26 22:25     ` Rob Herring
2018-03-23 14:38 ` [PATCH v2 4/7] dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings Yixun Lan
2018-03-23 14:38   ` Yixun Lan
2018-03-23 14:38   ` Yixun Lan
2018-03-23 14:38   ` Yixun Lan
2018-03-26 22:25   ` Rob Herring
2018-03-26 22:25     ` Rob Herring
2018-03-26 22:25     ` Rob Herring
2018-03-23 14:38 ` [PATCH v2 5/7] clk: meson-axg: Add AO Clock and Reset controller driver Yixun Lan
2018-03-23 14:38   ` Yixun Lan
2018-03-23 14:38   ` Yixun Lan
2018-03-23 14:38 ` [PATCH v2 6/7] arm64: dts: meson-axg: add AO clock driver DT info Yixun Lan
2018-03-23 14:38   ` Yixun Lan
2018-03-23 14:38   ` Yixun Lan
2018-03-23 14:38   ` Yixun Lan
2018-03-23 14:38 ` [PATCH v2 7/7] ARM64: dts: meson-axg: add an 32K alt aoclk Yixun Lan
2018-03-23 14:38   ` Yixun Lan
2018-03-23 14:38   ` Yixun Lan
2018-03-23 14:38   ` Yixun Lan
2018-03-27  9:00   ` Jerome Brunet [this message]
2018-03-27  9:00     ` Jerome Brunet
2018-03-27  9:00     ` Jerome Brunet
2018-03-27  9:00     ` Jerome Brunet

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