From: Michael Clark <mjc@sifive.com>
To: qemu-devel@nongnu.org, Peter Maydell <peter.maydell@linaro.org>
Cc: patches@groups.riscv.org, Michael Clark <mjc@sifive.com>,
Palmer Dabbelt <palmer@sifive.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Subject: [Qemu-devel] [PATCH v1 0/2] RISC-V: Important fixes for QEMU 2.12
Date: Tue, 27 Mar 2018 12:55:45 -0700 [thread overview]
Message-ID: <1522180547-22956-1-git-send-email-mjc@sifive.com> (raw)
This series includes changes that are considered important.
i.e. correct user-visible bugs that are exercised by common
operations such as -cpu list or -d in_asm
Michael Clark (2):
RISC-V: Convert cpu definition to future model
RISC-V: Fix incorrect disassembly for addiw
disas/riscv.c | 2 +-
target/riscv/cpu.c | 123 ++++++++++++++++++++++++++++++-----------------------
2 files changed, 70 insertions(+), 55 deletions(-)
--
2.7.0
next reply other threads:[~2018-03-27 19:56 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-27 19:55 Michael Clark [this message]
2018-03-27 19:55 ` [Qemu-devel] [PATCH v1 1/2] RISC-V: Convert cpu definition to future model Michael Clark
2018-03-28 4:38 ` Richard Henderson
2018-03-27 19:55 ` [Qemu-devel] [PATCH v1 2/2] RISC-V: Fix incorrect disassembly for addiw Michael Clark
2018-03-27 22:15 ` Philippe Mathieu-Daudé
2018-03-28 4:40 ` Richard Henderson
2018-03-31 7:33 ` [Qemu-devel] [PATCH v1 0/2] RISC-V: Important fixes for QEMU 2.12 no-reply
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