From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: Michael Clark <mjc@sifive.com>, qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Palmer Dabbelt <palmer@sifive.com>,
patches@groups.riscv.org
Subject: Re: [Qemu-devel] [PATCH v1 2/2] RISC-V: Fix incorrect disassembly for addiw
Date: Tue, 27 Mar 2018 19:15:50 -0300 [thread overview]
Message-ID: <37a9042b-1401-13dc-a062-eb0014ec2716@amsat.org> (raw)
In-Reply-To: <1522180547-22956-3-git-send-email-mjc@sifive.com>
On 03/27/2018 04:55 PM, Michael Clark wrote:
> This fixes a bug in the disassembler constraints used
> to lift instructions into pseudo-instructions, whereby
> addiw instructions are always lifted to sext.w instead
> of just lifting addiw with a zero immediate.
>
> An associated fix has been made to the metadata used to
> machine generate the disseasembler:
>
> https://github.com/michaeljclark/riscv-meta/
> commit/4a6b2f3898430768acfe201405224d2ea31e1477
>
> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> disas/riscv.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 3c17501..74ad16e 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -600,7 +600,7 @@ static const rvc_constraint rvcc_mv[] = { rvc_imm_eq_zero, rvc_end };
> static const rvc_constraint rvcc_not[] = { rvc_imm_eq_n1, rvc_end };
> static const rvc_constraint rvcc_neg[] = { rvc_rs1_eq_x0, rvc_end };
> static const rvc_constraint rvcc_negw[] = { rvc_rs1_eq_x0, rvc_end };
> -static const rvc_constraint rvcc_sext_w[] = { rvc_rs2_eq_x0, rvc_end };
> +static const rvc_constraint rvcc_sext_w[] = { rvc_imm_eq_zero, rvc_end };
> static const rvc_constraint rvcc_seqz[] = { rvc_imm_eq_p1, rvc_end };
> static const rvc_constraint rvcc_snez[] = { rvc_rs1_eq_x0, rvc_end };
> static const rvc_constraint rvcc_sltz[] = { rvc_rs2_eq_x0, rvc_end };
>
next prev parent reply other threads:[~2018-03-27 22:16 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-27 19:55 [Qemu-devel] [PATCH v1 0/2] RISC-V: Important fixes for QEMU 2.12 Michael Clark
2018-03-27 19:55 ` [Qemu-devel] [PATCH v1 1/2] RISC-V: Convert cpu definition to future model Michael Clark
2018-03-28 4:38 ` Richard Henderson
2018-03-27 19:55 ` [Qemu-devel] [PATCH v1 2/2] RISC-V: Fix incorrect disassembly for addiw Michael Clark
2018-03-27 22:15 ` Philippe Mathieu-Daudé [this message]
2018-03-28 4:40 ` Richard Henderson
2018-03-31 7:33 ` [Qemu-devel] [PATCH v1 0/2] RISC-V: Important fixes for QEMU 2.12 no-reply
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