From: Babu Moger <babu.moger@amd.com> To: mst@redhat.com, marcel.apfelbaum@gmail.com, pbonzini@redhat.com, rth@twiddle.net, ehabkost@redhat.com, mtosatti@redhat.com Cc: geoff@hostfission.com, babu.moger@amd.com, kash@tripleback.net, qemu-devel@nongnu.org, kvm@vger.kernel.org Subject: [PATCH v10 4/5] i386: Enable TOPOEXT feature on AMD EPYC CPU Date: Mon, 21 May 2018 20:41:14 -0400 [thread overview] Message-ID: <1526949675-106737-5-git-send-email-babu.moger@amd.com> (raw) In-Reply-To: <1526949675-106737-1-git-send-email-babu.moger@amd.com> Enable TOPOEXT feature on EPYC CPU. This is required to support hyperthreading on VM guests. Also extend xlevel to 0x8000001E. Disable TOPOEXT feature for legacy machines and also disable TOPOEXT feature if the config cannot be supported. Signed-off-by: Babu Moger <babu.moger@amd.com> --- include/hw/i386/pc.h | 4 ++++ target/i386/cpu.c | 37 +++++++++++++++++++++++++++++++++++-- 2 files changed, 39 insertions(+), 2 deletions(-) diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index a0c269f..9c8db3d 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -302,6 +302,10 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *); .driver = TYPE_X86_CPU,\ .property = "legacy-cache",\ .value = "on",\ + },{\ + .driver = "EPYC-" TYPE_X86_CPU,\ + .property = "topoext",\ + .value = "off",\ }, #define PC_COMPAT_2_11 \ diff --git a/target/i386/cpu.c b/target/i386/cpu.c index d9ccaad..d20b305 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -496,6 +496,20 @@ static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu, } /* + * Check if we can support this topology + * Fail if number of cores are beyond the supported config + * or nr_threads is more than 2 + */ +static int verify_topology(int nr_cores, int nr_threads) +{ + if ((nr_cores > (MAX_CORES_IN_NODE * MAX_NODES_EPYC)) || + (nr_threads > 2)) { + return 0; + } + return 1; +} + +/* * Definitions of the hardcoded cache entries we expose: * These are legacy cache values. If there is a need to change any * of these values please use builtin_x86_defs @@ -2541,7 +2555,8 @@ static X86CPUDefinition builtin_x86_defs[] = { .features[FEAT_8000_0001_ECX] = CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | - CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, + CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | + CPUID_EXT3_TOPOEXT, .features[FEAT_7_0_EBX] = CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | @@ -2586,7 +2601,8 @@ static X86CPUDefinition builtin_x86_defs[] = { .features[FEAT_8000_0001_ECX] = CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | - CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, + CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | + CPUID_EXT3_TOPOEXT, .features[FEAT_8000_0008_EBX] = CPUID_8000_0008_EBX_IBPB, .features[FEAT_7_0_EBX] = @@ -4166,6 +4182,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, break; case 0x8000001D: *eax = 0; + /* Check if we can support this topology */ + if (!verify_topology(cs->nr_cores, cs->nr_threads)) { + /* Disable topology extention */ + env->features[FEAT_8000_0001_ECX] &= !CPUID_EXT3_TOPOEXT; + break; + } switch (count) { case 0: /* L1 dcache info */ encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, cs, @@ -4190,6 +4212,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, break; case 0x8000001E: assert(cpu->core_id <= 255); + /* Check if we can support this topology */ + if (!verify_topology(cs->nr_cores, cs->nr_threads)) { + /* Disable topology extention */ + env->features[FEAT_8000_0001_ECX] &= !CPUID_EXT3_TOPOEXT; + break; + } encode_topo_cpuid8000001e(cs, cpu, eax, ebx, ecx, edx); break; @@ -4654,6 +4682,11 @@ static void x86_cpu_expand_features(X86CPU *cpu, Error **errp) x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); } + /* TOPOEXT feature requires 0x8000001E */ + if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) { + x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001E); + } + /* SEV requires CPUID[0x8000001F] */ if (sev_enabled()) { x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); -- 1.8.3.1
WARNING: multiple messages have this Message-ID (diff)
From: Babu Moger <babu.moger@amd.com> To: mst@redhat.com, marcel.apfelbaum@gmail.com, pbonzini@redhat.com, rth@twiddle.net, ehabkost@redhat.com, mtosatti@redhat.com Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, babu.moger@amd.com, kash@tripleback.net, geoff@hostfission.com Subject: [Qemu-devel] [PATCH v10 4/5] i386: Enable TOPOEXT feature on AMD EPYC CPU Date: Mon, 21 May 2018 20:41:14 -0400 [thread overview] Message-ID: <1526949675-106737-5-git-send-email-babu.moger@amd.com> (raw) In-Reply-To: <1526949675-106737-1-git-send-email-babu.moger@amd.com> Enable TOPOEXT feature on EPYC CPU. This is required to support hyperthreading on VM guests. Also extend xlevel to 0x8000001E. Disable TOPOEXT feature for legacy machines and also disable TOPOEXT feature if the config cannot be supported. Signed-off-by: Babu Moger <babu.moger@amd.com> --- include/hw/i386/pc.h | 4 ++++ target/i386/cpu.c | 37 +++++++++++++++++++++++++++++++++++-- 2 files changed, 39 insertions(+), 2 deletions(-) diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index a0c269f..9c8db3d 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -302,6 +302,10 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *); .driver = TYPE_X86_CPU,\ .property = "legacy-cache",\ .value = "on",\ + },{\ + .driver = "EPYC-" TYPE_X86_CPU,\ + .property = "topoext",\ + .value = "off",\ }, #define PC_COMPAT_2_11 \ diff --git a/target/i386/cpu.c b/target/i386/cpu.c index d9ccaad..d20b305 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -496,6 +496,20 @@ static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu, } /* + * Check if we can support this topology + * Fail if number of cores are beyond the supported config + * or nr_threads is more than 2 + */ +static int verify_topology(int nr_cores, int nr_threads) +{ + if ((nr_cores > (MAX_CORES_IN_NODE * MAX_NODES_EPYC)) || + (nr_threads > 2)) { + return 0; + } + return 1; +} + +/* * Definitions of the hardcoded cache entries we expose: * These are legacy cache values. If there is a need to change any * of these values please use builtin_x86_defs @@ -2541,7 +2555,8 @@ static X86CPUDefinition builtin_x86_defs[] = { .features[FEAT_8000_0001_ECX] = CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | - CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, + CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | + CPUID_EXT3_TOPOEXT, .features[FEAT_7_0_EBX] = CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | @@ -2586,7 +2601,8 @@ static X86CPUDefinition builtin_x86_defs[] = { .features[FEAT_8000_0001_ECX] = CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | - CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, + CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | + CPUID_EXT3_TOPOEXT, .features[FEAT_8000_0008_EBX] = CPUID_8000_0008_EBX_IBPB, .features[FEAT_7_0_EBX] = @@ -4166,6 +4182,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, break; case 0x8000001D: *eax = 0; + /* Check if we can support this topology */ + if (!verify_topology(cs->nr_cores, cs->nr_threads)) { + /* Disable topology extention */ + env->features[FEAT_8000_0001_ECX] &= !CPUID_EXT3_TOPOEXT; + break; + } switch (count) { case 0: /* L1 dcache info */ encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, cs, @@ -4190,6 +4212,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, break; case 0x8000001E: assert(cpu->core_id <= 255); + /* Check if we can support this topology */ + if (!verify_topology(cs->nr_cores, cs->nr_threads)) { + /* Disable topology extention */ + env->features[FEAT_8000_0001_ECX] &= !CPUID_EXT3_TOPOEXT; + break; + } encode_topo_cpuid8000001e(cs, cpu, eax, ebx, ecx, edx); break; @@ -4654,6 +4682,11 @@ static void x86_cpu_expand_features(X86CPU *cpu, Error **errp) x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); } + /* TOPOEXT feature requires 0x8000001E */ + if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) { + x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001E); + } + /* SEV requires CPUID[0x8000001F] */ if (sev_enabled()) { x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); -- 1.8.3.1
next prev parent reply other threads:[~2018-05-22 0:41 UTC|newest] Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-05-22 0:41 [PATCH v10 0/5] i386: Enable TOPOEXT to support hyperthreading on AMD CPU Babu Moger 2018-05-22 0:41 ` [Qemu-devel] " Babu Moger 2018-05-22 0:41 ` [PATCH v10 1/5] i386: Clean up cache CPUID code Babu Moger 2018-05-22 0:41 ` [Qemu-devel] " Babu Moger 2018-05-22 0:41 ` [PATCH v10 2/5] i386: Populate AMD Processor Cache Information for cpuid 0x8000001D Babu Moger 2018-05-22 0:41 ` [Qemu-devel] " Babu Moger 2018-05-22 1:32 ` Duran, Leo 2018-05-22 1:32 ` [Qemu-devel] " Duran, Leo 2018-05-22 13:32 ` Moger, Babu 2018-05-22 13:32 ` [Qemu-devel] " Moger, Babu 2018-05-22 14:03 ` Eduardo Habkost 2018-05-22 14:03 ` [Qemu-devel] " Eduardo Habkost 2018-05-23 16:18 ` Moger, Babu 2018-05-23 16:18 ` [Qemu-devel] " Moger, Babu 2018-05-22 13:54 ` Eduardo Habkost 2018-05-22 13:54 ` [Qemu-devel] " Eduardo Habkost 2018-05-23 18:16 ` Moger, Babu 2018-05-23 18:16 ` [Qemu-devel] " Moger, Babu 2018-05-22 0:41 ` [PATCH v10 3/5] i386: Add support for CPUID_8000_001E for AMD Babu Moger 2018-05-22 0:41 ` [Qemu-devel] " Babu Moger 2018-05-22 0:41 ` Babu Moger [this message] 2018-05-22 0:41 ` [Qemu-devel] [PATCH v10 4/5] i386: Enable TOPOEXT feature on AMD EPYC CPU Babu Moger 2018-05-22 0:41 ` [PATCH v10 5/5] i386: Remove generic SMT thread check Babu Moger 2018-05-22 0:41 ` [Qemu-devel] " Babu Moger
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