From: Aapo Vienamo <avienamo@nvidia.com> To: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Thierry Reding <thierry.reding@gmail.com>, Jonathan Hunter <jonathanh@nvidia.com>, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org, Aapo Vienamo <avienamo@nvidia.com> Subject: [PATCH v4 2/4] clk: tegra: refactor 7.1 div calculation Date: Mon, 9 Jul 2018 19:38:56 +0300 [thread overview] Message-ID: <1531154338-3998-3-git-send-email-avienamo@nvidia.com> (raw) In-Reply-To: <1531154338-3998-1-git-send-email-avienamo@nvidia.com> From: Peter De Schrijver <pdeschrijver@nvidia.com> Move this to a separate file so it can be used to calculate the sdmmc clock dividers. Signed-off-by: Peter De-Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> --- drivers/clk/tegra/Makefile | 1 + drivers/clk/tegra/clk-divider.c | 30 +++++----------------------- drivers/clk/tegra/clk.h | 3 +++ drivers/clk/tegra/div71.c | 43 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 52 insertions(+), 25 deletions(-) create mode 100644 drivers/clk/tegra/div71.c diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile index b716923..6d4f563 100644 --- a/drivers/clk/tegra/Makefile +++ b/drivers/clk/tegra/Makefile @@ -24,3 +24,4 @@ obj-$(CONFIG_ARCH_TEGRA_132_SOC) += clk-tegra124.o obj-y += cvb.o obj-$(CONFIG_ARCH_TEGRA_210_SOC) += clk-tegra210.o obj-$(CONFIG_CLK_TEGRA_BPMP) += clk-bpmp.o +obj-y += div71.o diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c index 16e0aee..ad87858 100644 --- a/drivers/clk/tegra/clk-divider.c +++ b/drivers/clk/tegra/clk-divider.c @@ -32,35 +32,15 @@ static int get_div(struct tegra_clk_frac_div *divider, unsigned long rate, unsigned long parent_rate) { - u64 divider_ux1 = parent_rate; - u8 flags = divider->flags; - int mul; - - if (!rate) - return 0; - - mul = get_mul(divider); - - if (!(flags & TEGRA_DIVIDER_INT)) - divider_ux1 *= mul; - - if (flags & TEGRA_DIVIDER_ROUND_UP) - divider_ux1 += rate - 1; - - do_div(divider_ux1, rate); - - if (flags & TEGRA_DIVIDER_INT) - divider_ux1 *= mul; + int div; - divider_ux1 -= mul; + div = div71_get(rate, parent_rate, divider->width, divider->frac_width, + divider->flags); - if ((s64)divider_ux1 < 0) + if (div < 0) return 0; - if (divider_ux1 > get_max_div(divider)) - return get_max_div(divider); - - return divider_ux1; + return div; } static unsigned long clk_frac_div_recalc_rate(struct clk_hw *hw, diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index e3b9c22..149cc70 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -812,6 +812,9 @@ extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table; int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll); u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate); int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div); +int div71_get(unsigned long rate, unsigned parent_rate, u8 width, + u8 frac_width, u8 flags); + /* Combined read fence with delay */ #define fence_udelay(delay, reg) \ diff --git a/drivers/clk/tegra/div71.c b/drivers/clk/tegra/div71.c new file mode 100644 index 0000000..1eecc84 --- /dev/null +++ b/drivers/clk/tegra/div71.c @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. + */ + +#include <asm/div64.h> + +#include "clk.h" + +#define div_mask(w) ((1 << (w)) - 1) + +int div71_get(unsigned long rate, unsigned parent_rate, u8 width, + u8 frac_width, u8 flags) +{ + u64 divider_ux1 = parent_rate; + int mul; + + if (!rate) + return 0; + + mul = 1 << frac_width; + + if (!(flags & TEGRA_DIVIDER_INT)) + divider_ux1 *= mul; + + if (flags & TEGRA_DIVIDER_ROUND_UP) + divider_ux1 += rate - 1; + + do_div(divider_ux1, rate); + + if (flags & TEGRA_DIVIDER_INT) + divider_ux1 *= mul; + + if (divider_ux1 < mul) + return 0; + + divider_ux1 -= mul; + + if (divider_ux1 > div_mask(width)) + return div_mask(width); + + return divider_ux1; +} -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Aapo Vienamo <avienamo@nvidia.com> To: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Thierry Reding <thierry.reding@gmail.com>, Jonathan Hunter <jonathanh@nvidia.com>, <linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org>, <linux-tegra@vger.kernel.org>, Aapo Vienamo <avienamo@nvidia.com> Subject: [PATCH v4 2/4] clk: tegra: refactor 7.1 div calculation Date: Mon, 9 Jul 2018 19:38:56 +0300 [thread overview] Message-ID: <1531154338-3998-3-git-send-email-avienamo@nvidia.com> (raw) In-Reply-To: <1531154338-3998-1-git-send-email-avienamo@nvidia.com> From: Peter De Schrijver <pdeschrijver@nvidia.com> Move this to a separate file so it can be used to calculate the sdmmc clock dividers. Signed-off-by: Peter De-Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> --- drivers/clk/tegra/Makefile | 1 + drivers/clk/tegra/clk-divider.c | 30 +++++----------------------- drivers/clk/tegra/clk.h | 3 +++ drivers/clk/tegra/div71.c | 43 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 52 insertions(+), 25 deletions(-) create mode 100644 drivers/clk/tegra/div71.c diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile index b716923..6d4f563 100644 --- a/drivers/clk/tegra/Makefile +++ b/drivers/clk/tegra/Makefile @@ -24,3 +24,4 @@ obj-$(CONFIG_ARCH_TEGRA_132_SOC) += clk-tegra124.o obj-y += cvb.o obj-$(CONFIG_ARCH_TEGRA_210_SOC) += clk-tegra210.o obj-$(CONFIG_CLK_TEGRA_BPMP) += clk-bpmp.o +obj-y += div71.o diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c index 16e0aee..ad87858 100644 --- a/drivers/clk/tegra/clk-divider.c +++ b/drivers/clk/tegra/clk-divider.c @@ -32,35 +32,15 @@ static int get_div(struct tegra_clk_frac_div *divider, unsigned long rate, unsigned long parent_rate) { - u64 divider_ux1 = parent_rate; - u8 flags = divider->flags; - int mul; - - if (!rate) - return 0; - - mul = get_mul(divider); - - if (!(flags & TEGRA_DIVIDER_INT)) - divider_ux1 *= mul; - - if (flags & TEGRA_DIVIDER_ROUND_UP) - divider_ux1 += rate - 1; - - do_div(divider_ux1, rate); - - if (flags & TEGRA_DIVIDER_INT) - divider_ux1 *= mul; + int div; - divider_ux1 -= mul; + div = div71_get(rate, parent_rate, divider->width, divider->frac_width, + divider->flags); - if ((s64)divider_ux1 < 0) + if (div < 0) return 0; - if (divider_ux1 > get_max_div(divider)) - return get_max_div(divider); - - return divider_ux1; + return div; } static unsigned long clk_frac_div_recalc_rate(struct clk_hw *hw, diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index e3b9c22..149cc70 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -812,6 +812,9 @@ extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table; int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll); u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate); int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div); +int div71_get(unsigned long rate, unsigned parent_rate, u8 width, + u8 frac_width, u8 flags); + /* Combined read fence with delay */ #define fence_udelay(delay, reg) \ diff --git a/drivers/clk/tegra/div71.c b/drivers/clk/tegra/div71.c new file mode 100644 index 0000000..1eecc84 --- /dev/null +++ b/drivers/clk/tegra/div71.c @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. + */ + +#include <asm/div64.h> + +#include "clk.h" + +#define div_mask(w) ((1 << (w)) - 1) + +int div71_get(unsigned long rate, unsigned parent_rate, u8 width, + u8 frac_width, u8 flags) +{ + u64 divider_ux1 = parent_rate; + int mul; + + if (!rate) + return 0; + + mul = 1 << frac_width; + + if (!(flags & TEGRA_DIVIDER_INT)) + divider_ux1 *= mul; + + if (flags & TEGRA_DIVIDER_ROUND_UP) + divider_ux1 += rate - 1; + + do_div(divider_ux1, rate); + + if (flags & TEGRA_DIVIDER_INT) + divider_ux1 *= mul; + + if (divider_ux1 < mul) + return 0; + + divider_ux1 -= mul; + + if (divider_ux1 > div_mask(width)) + return div_mask(width); + + return divider_ux1; +} -- 2.7.4
next prev parent reply other threads:[~2018-07-09 16:38 UTC|newest] Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-07-09 16:38 [PATCH v4 0/4] Multiplex sdmmc low jitter clock path Aapo Vienamo 2018-07-09 16:38 ` Aapo Vienamo 2018-07-09 16:38 ` [PATCH v4 1/4] clk: tegra: Fix includes required by fence_udelay() Aapo Vienamo 2018-07-09 16:38 ` Aapo Vienamo 2018-07-09 16:38 ` Aapo Vienamo [this message] 2018-07-09 16:38 ` [PATCH v4 2/4] clk: tegra: refactor 7.1 div calculation Aapo Vienamo 2018-07-10 16:17 ` Jon Hunter 2018-07-10 16:17 ` Jon Hunter 2018-07-11 8:00 ` Peter De Schrijver 2018-07-11 8:00 ` Peter De Schrijver 2018-07-11 8:42 ` Jon Hunter 2018-07-11 8:42 ` Jon Hunter 2018-07-11 11:17 ` Peter De Schrijver 2018-07-11 11:17 ` Peter De Schrijver 2018-07-11 15:14 ` Jon Hunter 2018-07-11 15:14 ` Jon Hunter 2018-07-12 7:44 ` Aapo Vienamo 2018-07-12 7:44 ` Aapo Vienamo 2018-07-09 16:38 ` [PATCH v4 3/4] clk: tegra: Add sdmmc mux divider clock Aapo Vienamo 2018-07-09 16:38 ` Aapo Vienamo 2018-07-09 16:38 ` [PATCH v4 4/4] clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks Aapo Vienamo 2018-07-09 16:38 ` Aapo Vienamo 2018-07-10 7:00 ` [PATCH v4 0/4] Multiplex sdmmc low jitter clock path Peter De Schrijver 2018-07-10 7:00 ` Peter De Schrijver
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=1531154338-3998-3-git-send-email-avienamo@nvidia.com \ --to=avienamo@nvidia.com \ --cc=jonathanh@nvidia.com \ --cc=linux-clk@vger.kernel.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-tegra@vger.kernel.org \ --cc=mturquette@baylibre.com \ --cc=pdeschrijver@nvidia.com \ --cc=pgaikwad@nvidia.com \ --cc=sboyd@kernel.org \ --cc=thierry.reding@gmail.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.