Re: [PATCH 1/3] drm/i915: Prepare for larger CSB status FIFO size

From: Chris Wilson <chris@chris-wilson.co.uk>
To: Mika Kuoppala <mika.kuoppala@linux.intel.com>,
	intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/3] drm/i915: Prepare for larger CSB status FIFO size
Date: Tue, 27 Nov 2018 17:46:43 +0000	[thread overview]
Message-ID: <154334080300.11623.1481147864619869213@skylake-alporthouse-com> (raw)
In-Reply-To: <20181127173845.17403-1-mika.kuoppala@linux.intel.com>

Quoting Mika Kuoppala (2018-11-27 17:38:43)
>  static void reset_csb_pointers(struct intel_engine_execlists *execlists)
>  {
> +       u32 reset_val;
>         /*
>          * After a reset, the HW starts writing into CSB entry [0]. We
>          * therefore have to set our HEAD pointer back one entry so that
> @@ -776,8 +777,19 @@ static void reset_csb_pointers(struct intel_engine_execlists *execlists)
>          * inline comparison of our cached head position against the last HW
>          * write works even before the first interrupt.
>          */
> -       execlists->csb_head = execlists->csb_write_reset;
> -       WRITE_ONCE(*execlists->csb_write, execlists->csb_write_reset);
> +       execlists->csb_head = execlists->csb_entries - 1;
> +
> +       if (execlists_mmio_mode(execlists)) {
> +               const u32 mask = execlists->csb_entries == GEN8_CSB_ENTRIES ?
> +                       GEN8_CSB_WRITE_PTR_MASK :
> +                       GEN11_CSB_WRITE_PTR_MASK;
> +
> +               reset_val = _MASKED_FIELD(mask, execlists->csb_head);
> +       } else {
> +               reset_val = execlists->csb_head;
> +       }

Think: did I need to change this?
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx