From: Aisheng Dong <aisheng.dong@nxp.com> To: "linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org> Cc: "linux-arm-kernel@lists.infradead.org" <linux-arm-kernel@lists.infradead.org>, "sboyd@kernel.org" <sboyd@kernel.org>, "mturquette@baylibre.com" <mturquette@baylibre.com>, "shawnguo@kernel.org" <shawnguo@kernel.org>, Fabio Estevam <fabio.estevam@nxp.com>, dl-linux-imx <linux-imx@nxp.com>, "kernel@pengutronix.de" <kernel@pengutronix.de>, Aisheng Dong <aisheng.dong@nxp.com> Subject: [PATCH V12 4/5] clk: imx: add lpcg clock support Date: Thu, 13 Dec 2018 15:43:01 +0000 [thread overview] Message-ID: <1544715442-8902-5-git-send-email-aisheng.dong@nxp.com> (raw) In-Reply-To: <1544715442-8902-1-git-send-email-aisheng.dong@nxp.com> The Low-Power Clock Gate (LPCG) modules contain a local programming model to control the clock gates for the peripherals. An LPCG module is used to locally gate the clocks for the associated peripheral. And they're bedind the SCU clock. Cc: Stephen Boyd <sboyd@kernel.org> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> --- ChangeLog: v9->v12: * no changes v8->v9: * use readl_relaxed() as it does not need insert barrier * a small code logic improvement suggested by Stephen v7->v8: * add doc for struct clk_lpcg_scu * remove unneccessary reg checking v6: separate from [PATCH V5 5/9] clk: imx: scu: add scu clock gate --- drivers/clk/imx/Makefile | 3 +- drivers/clk/imx/clk-lpcg-scu.c | 114 +++++++++++++++++++++++++++++++++++++++++ drivers/clk/imx/clk-scu.h | 3 ++ 3 files changed, 119 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/imx/clk-lpcg-scu.c diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 31c19c5..657d82b5 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -21,7 +21,8 @@ obj-$(CONFIG_MXC_CLK) += \ clk-sccg-pll.o obj-$(CONFIG_MXC_CLK_SCU) += \ - clk-scu.o + clk-scu.o \ + clk-lpcg-scu.o obj-$(CONFIG_SOC_IMX1) += clk-imx1.o obj-$(CONFIG_SOC_IMX21) += clk-imx21.o diff --git a/drivers/clk/imx/clk-lpcg-scu.c b/drivers/clk/imx/clk-lpcg-scu.c new file mode 100644 index 0000000..fbf3416 --- /dev/null +++ b/drivers/clk/imx/clk-lpcg-scu.c @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Dong Aisheng <aisheng.dong@nxp.com> + */ + +#include <linux/clk-provider.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/slab.h> +#include <linux/spinlock.h> + +static DEFINE_SPINLOCK(imx_lpcg_scu_lock); + +#define CLK_GATE_SCU_LPCG_MASK 0x3 +#define CLK_GATE_SCU_LPCG_HW_SEL BIT(0) +#define CLK_GATE_SCU_LPCG_SW_SEL BIT(1) + +/* + * struct clk_lpcg_scu - Description of LPCG clock + * + * @hw: clk_hw of this LPCG + * @reg: register of this LPCG clock + * @bit_idx: bit index of this LPCG clock + * @hw_gate: HW auto gate enable + * + * This structure describes one LPCG clock + */ +struct clk_lpcg_scu { + struct clk_hw hw; + void __iomem *reg; + u8 bit_idx; + bool hw_gate; +}; + +#define to_clk_lpcg_scu(_hw) container_of(_hw, struct clk_lpcg_scu, hw) + +static int clk_lpcg_scu_enable(struct clk_hw *hw) +{ + struct clk_lpcg_scu *clk = to_clk_lpcg_scu(hw); + unsigned long flags; + u32 reg, val; + + spin_lock_irqsave(&imx_lpcg_scu_lock, flags); + + reg = readl_relaxed(clk->reg); + reg &= ~(CLK_GATE_SCU_LPCG_MASK << clk->bit_idx); + + val = CLK_GATE_SCU_LPCG_SW_SEL; + if (clk->hw_gate) + val |= CLK_GATE_SCU_LPCG_HW_SEL; + + reg |= val << clk->bit_idx; + writel(reg, clk->reg); + + spin_unlock_irqrestore(&imx_lpcg_scu_lock, flags); + + return 0; +} + +static void clk_lpcg_scu_disable(struct clk_hw *hw) +{ + struct clk_lpcg_scu *clk = to_clk_lpcg_scu(hw); + unsigned long flags; + u32 reg; + + spin_lock_irqsave(&imx_lpcg_scu_lock, flags); + + reg = readl_relaxed(clk->reg); + reg &= ~(CLK_GATE_SCU_LPCG_MASK << clk->bit_idx); + writel(reg, clk->reg); + + spin_unlock_irqrestore(&imx_lpcg_scu_lock, flags); +} + +static const struct clk_ops clk_lpcg_scu_ops = { + .enable = clk_lpcg_scu_enable, + .disable = clk_lpcg_scu_disable, +}; + +struct clk_hw *imx_clk_lpcg_scu(const char *name, const char *parent_name, + unsigned long flags, void __iomem *reg, + u8 bit_idx, bool hw_gate) +{ + struct clk_lpcg_scu *clk; + struct clk_init_data init; + struct clk_hw *hw; + int ret; + + clk = kzalloc(sizeof(*clk), GFP_KERNEL); + if (!clk) + return ERR_PTR(-ENOMEM); + + clk->reg = reg; + clk->bit_idx = bit_idx; + clk->hw_gate = hw_gate; + + init.name = name; + init.ops = &clk_lpcg_scu_ops; + init.flags = CLK_SET_RATE_PARENT | flags; + init.parent_names = parent_name ? &parent_name : NULL; + init.num_parents = parent_name ? 1 : 0; + + clk->hw.init = &init; + + hw = &clk->hw; + ret = clk_hw_register(NULL, hw); + if (ret) { + kfree(clk); + hw = ERR_PTR(ret); + } + + return hw; +} diff --git a/drivers/clk/imx/clk-scu.h b/drivers/clk/imx/clk-scu.h index 309b4de..52c1746 100644 --- a/drivers/clk/imx/clk-scu.h +++ b/drivers/clk/imx/clk-scu.h @@ -12,4 +12,7 @@ int imx_clk_scu_init(void); struct clk_hw *imx_clk_scu(const char *name, u32 rsrc_id, u8 clk_type); +struct clk_hw *imx_clk_lpcg_scu(const char *name, const char *parent_name, + unsigned long flags, void __iomem *reg, + u8 bit_idx, bool hw_gate); #endif -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Aisheng Dong <aisheng.dong@nxp.com> To: "linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org> Cc: Aisheng Dong <aisheng.dong@nxp.com>, "sboyd@kernel.org" <sboyd@kernel.org>, "mturquette@baylibre.com" <mturquette@baylibre.com>, dl-linux-imx <linux-imx@nxp.com>, "kernel@pengutronix.de" <kernel@pengutronix.de>, Fabio Estevam <fabio.estevam@nxp.com>, "shawnguo@kernel.org" <shawnguo@kernel.org>, "linux-arm-kernel@lists.infradead.org" <linux-arm-kernel@lists.infradead.org> Subject: [PATCH V12 4/5] clk: imx: add lpcg clock support Date: Thu, 13 Dec 2018 15:43:01 +0000 [thread overview] Message-ID: <1544715442-8902-5-git-send-email-aisheng.dong@nxp.com> (raw) In-Reply-To: <1544715442-8902-1-git-send-email-aisheng.dong@nxp.com> The Low-Power Clock Gate (LPCG) modules contain a local programming model to control the clock gates for the peripherals. An LPCG module is used to locally gate the clocks for the associated peripheral. And they're bedind the SCU clock. Cc: Stephen Boyd <sboyd@kernel.org> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> --- ChangeLog: v9->v12: * no changes v8->v9: * use readl_relaxed() as it does not need insert barrier * a small code logic improvement suggested by Stephen v7->v8: * add doc for struct clk_lpcg_scu * remove unneccessary reg checking v6: separate from [PATCH V5 5/9] clk: imx: scu: add scu clock gate --- drivers/clk/imx/Makefile | 3 +- drivers/clk/imx/clk-lpcg-scu.c | 114 +++++++++++++++++++++++++++++++++++++++++ drivers/clk/imx/clk-scu.h | 3 ++ 3 files changed, 119 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/imx/clk-lpcg-scu.c diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 31c19c5..657d82b5 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -21,7 +21,8 @@ obj-$(CONFIG_MXC_CLK) += \ clk-sccg-pll.o obj-$(CONFIG_MXC_CLK_SCU) += \ - clk-scu.o + clk-scu.o \ + clk-lpcg-scu.o obj-$(CONFIG_SOC_IMX1) += clk-imx1.o obj-$(CONFIG_SOC_IMX21) += clk-imx21.o diff --git a/drivers/clk/imx/clk-lpcg-scu.c b/drivers/clk/imx/clk-lpcg-scu.c new file mode 100644 index 0000000..fbf3416 --- /dev/null +++ b/drivers/clk/imx/clk-lpcg-scu.c @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Dong Aisheng <aisheng.dong@nxp.com> + */ + +#include <linux/clk-provider.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/slab.h> +#include <linux/spinlock.h> + +static DEFINE_SPINLOCK(imx_lpcg_scu_lock); + +#define CLK_GATE_SCU_LPCG_MASK 0x3 +#define CLK_GATE_SCU_LPCG_HW_SEL BIT(0) +#define CLK_GATE_SCU_LPCG_SW_SEL BIT(1) + +/* + * struct clk_lpcg_scu - Description of LPCG clock + * + * @hw: clk_hw of this LPCG + * @reg: register of this LPCG clock + * @bit_idx: bit index of this LPCG clock + * @hw_gate: HW auto gate enable + * + * This structure describes one LPCG clock + */ +struct clk_lpcg_scu { + struct clk_hw hw; + void __iomem *reg; + u8 bit_idx; + bool hw_gate; +}; + +#define to_clk_lpcg_scu(_hw) container_of(_hw, struct clk_lpcg_scu, hw) + +static int clk_lpcg_scu_enable(struct clk_hw *hw) +{ + struct clk_lpcg_scu *clk = to_clk_lpcg_scu(hw); + unsigned long flags; + u32 reg, val; + + spin_lock_irqsave(&imx_lpcg_scu_lock, flags); + + reg = readl_relaxed(clk->reg); + reg &= ~(CLK_GATE_SCU_LPCG_MASK << clk->bit_idx); + + val = CLK_GATE_SCU_LPCG_SW_SEL; + if (clk->hw_gate) + val |= CLK_GATE_SCU_LPCG_HW_SEL; + + reg |= val << clk->bit_idx; + writel(reg, clk->reg); + + spin_unlock_irqrestore(&imx_lpcg_scu_lock, flags); + + return 0; +} + +static void clk_lpcg_scu_disable(struct clk_hw *hw) +{ + struct clk_lpcg_scu *clk = to_clk_lpcg_scu(hw); + unsigned long flags; + u32 reg; + + spin_lock_irqsave(&imx_lpcg_scu_lock, flags); + + reg = readl_relaxed(clk->reg); + reg &= ~(CLK_GATE_SCU_LPCG_MASK << clk->bit_idx); + writel(reg, clk->reg); + + spin_unlock_irqrestore(&imx_lpcg_scu_lock, flags); +} + +static const struct clk_ops clk_lpcg_scu_ops = { + .enable = clk_lpcg_scu_enable, + .disable = clk_lpcg_scu_disable, +}; + +struct clk_hw *imx_clk_lpcg_scu(const char *name, const char *parent_name, + unsigned long flags, void __iomem *reg, + u8 bit_idx, bool hw_gate) +{ + struct clk_lpcg_scu *clk; + struct clk_init_data init; + struct clk_hw *hw; + int ret; + + clk = kzalloc(sizeof(*clk), GFP_KERNEL); + if (!clk) + return ERR_PTR(-ENOMEM); + + clk->reg = reg; + clk->bit_idx = bit_idx; + clk->hw_gate = hw_gate; + + init.name = name; + init.ops = &clk_lpcg_scu_ops; + init.flags = CLK_SET_RATE_PARENT | flags; + init.parent_names = parent_name ? &parent_name : NULL; + init.num_parents = parent_name ? 1 : 0; + + clk->hw.init = &init; + + hw = &clk->hw; + ret = clk_hw_register(NULL, hw); + if (ret) { + kfree(clk); + hw = ERR_PTR(ret); + } + + return hw; +} diff --git a/drivers/clk/imx/clk-scu.h b/drivers/clk/imx/clk-scu.h index 309b4de..52c1746 100644 --- a/drivers/clk/imx/clk-scu.h +++ b/drivers/clk/imx/clk-scu.h @@ -12,4 +12,7 @@ int imx_clk_scu_init(void); struct clk_hw *imx_clk_scu(const char *name, u32 rsrc_id, u8 clk_type); +struct clk_hw *imx_clk_lpcg_scu(const char *name, const char *parent_name, + unsigned long flags, void __iomem *reg, + u8 bit_idx, bool hw_gate); #endif -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2018-12-13 15:43 UTC|newest] Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-12-13 15:42 [PATCH V12 0/5] clk: imx: add imx8qxp clock support Aisheng Dong 2018-12-13 15:42 ` Aisheng Dong 2018-12-13 15:42 ` [PATCH V12 1/5] clk: imx: add configuration option for mmio clks Aisheng Dong 2018-12-13 15:42 ` Aisheng Dong 2018-12-14 21:08 ` Stephen Boyd 2018-12-14 21:08 ` Stephen Boyd 2018-12-13 15:42 ` [PATCH V12 2/5] clk: imx: add scu clock common part Aisheng Dong 2018-12-13 15:42 ` Aisheng Dong 2018-12-14 21:08 ` Stephen Boyd 2018-12-14 21:08 ` Stephen Boyd 2018-12-13 15:42 ` [PATCH V12 3/5] clk: imx: add imx8qxp clk driver Aisheng Dong 2018-12-13 15:42 ` Aisheng Dong 2018-12-14 21:09 ` Stephen Boyd 2018-12-14 21:09 ` Stephen Boyd 2018-12-13 15:43 ` Aisheng Dong [this message] 2018-12-13 15:43 ` [PATCH V12 4/5] clk: imx: add lpcg clock support Aisheng Dong 2018-12-14 21:09 ` Stephen Boyd 2018-12-14 21:09 ` Stephen Boyd 2018-12-13 15:43 ` [PATCH V12 5/5] clk: imx: add imx8qxp lpcg driver Aisheng Dong 2018-12-13 15:43 ` Aisheng Dong 2018-12-14 21:09 ` Stephen Boyd 2018-12-14 21:09 ` Stephen Boyd 2018-12-14 2:05 ` [PATCH V12 0/5] clk: imx: add imx8qxp clock support Shawn Guo 2018-12-14 2:05 ` Shawn Guo 2018-12-14 2:17 ` Aisheng Dong 2018-12-14 2:17 ` Aisheng Dong 2018-12-14 3:19 ` Shawn Guo 2018-12-14 3:19 ` Shawn Guo 2018-12-14 3:37 ` Aisheng Dong 2018-12-14 3:37 ` Aisheng Dong 2018-12-14 3:56 ` Shawn Guo 2018-12-14 3:56 ` Shawn Guo 2018-12-14 4:57 ` Aisheng Dong 2018-12-14 4:57 ` Aisheng Dong 2018-12-14 5:30 ` Shawn Guo 2018-12-14 5:30 ` Shawn Guo 2018-12-14 5:38 ` Aisheng Dong 2018-12-14 5:38 ` Aisheng Dong 2018-12-14 6:07 ` Stephen Boyd 2018-12-14 6:07 ` Stephen Boyd 2018-12-14 6:15 ` Stephen Boyd 2018-12-14 6:15 ` Stephen Boyd 2018-12-14 6:16 ` Aisheng Dong 2018-12-14 6:16 ` Aisheng Dong 2018-12-14 6:15 ` Aisheng Dong 2018-12-14 6:15 ` Aisheng Dong 2018-12-14 5:44 ` Stephen Boyd 2018-12-14 5:44 ` Stephen Boyd
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