From: Stephen Boyd <sboyd@kernel.org>
To: Matthias Brugger <matthias.bgg@gmail.com>,
Nicolas Boichat <drinkcat@chromium.org>,
Rob Herring <robh@kernel.org>,
Stephen Boyd <sboyd@codeaurora.org>,
Weiyi Lu <weiyi.lu@mediatek.com>
Cc: James Liao <jamesjj.liao@mediatek.com>,
Fan Chen <fan.chen@mediatek.com>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
linux-clk@vger.kernel.org, srv_heupstream@mediatek.com,
stable@vger.kernel.org, Weiyi Lu <weiyi.lu@mediatek.com>
Subject: Re: [PATCH v3 08/12] clk: mediatek: Add MT8183 clock support
Date: Fri, 14 Dec 2018 13:59:52 -0800 [thread overview]
Message-ID: <154482479243.19322.7465842539016312943@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <20181210073240.32278-10-weiyi.lu@mediatek.com>
Quoting Weiyi Lu (2018-12-09 23:32:36)
> + "apll2_ck"
> +};
> +
> +static const struct mtk_mux top_muxes[] = {
> + /* CLK_CFG_0 */
> + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_AXI, "axi_sel",
> + axi_parents, 0x40,
> + 0x44, 0x48, 0, 2, 7, 0x004, 0, CLK_IS_CRITICAL),
Please document why CLK_IS_CRITICAL is being used everywhere it's used.
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MM, "mm_sel",
> + mm_parents, 0x40,
> + 0x44, 0x48, 8, 3, 15, 0x004, 1),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IMG, "img_sel",
> + img_parents, 0x40,
> + 0x44, 0x48, 16, 3, 23, 0x004, 2),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAM, "cam_sel",
WARNING: multiple messages have this Message-ID (diff)
From: Stephen Boyd <sboyd@kernel.org>
To: Matthias Brugger <matthias.bgg@gmail.com>,
Nicolas Boichat <drinkcat@chromium.org>,
Rob Herring <robh@kernel.org>,
Stephen Boyd <sboyd@codeaurora.org>
Cc: James Liao <jamesjj.liao@mediatek.com>,
Fan Chen <fan.chen@mediatek.com>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
linux-clk@vger.kernel.org, srv_heupstream@mediatek.com,
stable@vger.kernel.org, Weiyi Lu <weiyi.lu@mediatek.com>
Subject: Re: [PATCH v3 08/12] clk: mediatek: Add MT8183 clock support
Date: Fri, 14 Dec 2018 13:59:52 -0800 [thread overview]
Message-ID: <154482479243.19322.7465842539016312943@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <20181210073240.32278-10-weiyi.lu@mediatek.com>
Quoting Weiyi Lu (2018-12-09 23:32:36)
> + "apll2_ck"
> +};
> +
> +static const struct mtk_mux top_muxes[] = {
> + /* CLK_CFG_0 */
> + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_AXI, "axi_sel",
> + axi_parents, 0x40,
> + 0x44, 0x48, 0, 2, 7, 0x004, 0, CLK_IS_CRITICAL),
Please document why CLK_IS_CRITICAL is being used everywhere it's used.
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MM, "mm_sel",
> + mm_parents, 0x40,
> + 0x44, 0x48, 8, 3, 15, 0x004, 1),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IMG, "img_sel",
> + img_parents, 0x40,
> + 0x44, 0x48, 16, 3, 23, 0x004, 2),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAM, "cam_sel",
WARNING: multiple messages have this Message-ID (diff)
From: Stephen Boyd <sboyd@kernel.org>
To: Matthias Brugger <matthias.bgg@gmail.com>,
Nicolas Boichat <drinkcat@chromium.org>,
Rob Herring <robh@kernel.org>,
Stephen Boyd <sboyd@codeaurora.org>,
Weiyi Lu <weiyi.lu@mediatek.com>
Cc: James Liao <jamesjj.liao@mediatek.com>,
Weiyi Lu <weiyi.lu@mediatek.com>,
srv_heupstream@mediatek.com, linux-kernel@vger.kernel.org,
stable@vger.kernel.org, Fan Chen <fan.chen@mediatek.com>,
linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v3 08/12] clk: mediatek: Add MT8183 clock support
Date: Fri, 14 Dec 2018 13:59:52 -0800 [thread overview]
Message-ID: <154482479243.19322.7465842539016312943@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <20181210073240.32278-10-weiyi.lu@mediatek.com>
Quoting Weiyi Lu (2018-12-09 23:32:36)
> + "apll2_ck"
> +};
> +
> +static const struct mtk_mux top_muxes[] = {
> + /* CLK_CFG_0 */
> + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_AXI, "axi_sel",
> + axi_parents, 0x40,
> + 0x44, 0x48, 0, 2, 7, 0x004, 0, CLK_IS_CRITICAL),
Please document why CLK_IS_CRITICAL is being used everywhere it's used.
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MM, "mm_sel",
> + mm_parents, 0x40,
> + 0x44, 0x48, 8, 3, 15, 0x004, 1),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IMG, "img_sel",
> + img_parents, 0x40,
> + 0x44, 0x48, 16, 3, 23, 0x004, 2),
> + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAM, "cam_sel",
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next prev parent reply other threads:[~2018-12-14 21:59 UTC|newest]
Thread overview: 81+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-10 7:32 [PATCH v3 00/11] Mediatek MT8183 clock and scpsys support Weiyi Lu
2018-12-10 7:32 ` Weiyi Lu
2018-12-10 7:32 ` Weiyi Lu
2018-12-10 7:32 ` [PATCH v3 00/12] " Weiyi Lu
2018-12-10 7:32 ` Weiyi Lu
2018-12-10 7:32 ` Weiyi Lu
2018-12-10 7:32 ` [PATCH v3 01/12] clk: mediatek: fixup: Disable tuner_en before change PLL rate Weiyi Lu
2018-12-10 7:32 ` Weiyi Lu
2018-12-10 7:32 ` Weiyi Lu
2018-12-14 21:57 ` Stephen Boyd
2018-12-14 21:57 ` Stephen Boyd
2018-12-14 21:57 ` Stephen Boyd
2019-02-01 8:21 ` Weiyi Lu
2019-02-01 8:21 ` Weiyi Lu
2019-02-01 8:21 ` Weiyi Lu
2018-12-10 7:32 ` [PATCH v3 02/12] clk: mediatek: add new clkmux register API Weiyi Lu
2018-12-10 7:32 ` Weiyi Lu
2018-12-10 7:32 ` Weiyi Lu
2018-12-10 12:30 ` Nicolas Boichat
2018-12-10 12:30 ` Nicolas Boichat
2019-02-01 8:22 ` Weiyi Lu
2019-02-01 8:22 ` Weiyi Lu
2019-02-01 8:22 ` Weiyi Lu
2018-12-10 7:32 ` [PATCH v3 03/12] clk: mediatek: add configurable pcwibits and fmin to mtk_pll_data Weiyi Lu
2018-12-10 7:32 ` Weiyi Lu
2018-12-10 7:32 ` Weiyi Lu
2018-12-14 22:02 ` Stephen Boyd
2018-12-14 22:02 ` Stephen Boyd
2018-12-14 22:02 ` Stephen Boyd
2019-02-01 8:22 ` Weiyi Lu
2019-02-01 8:22 ` Weiyi Lu
2019-02-01 8:22 ` Weiyi Lu
2018-12-10 7:32 ` [PATCH v3 04/12] soc: mediatek: add new flow for mtcmos power Weiyi Lu
2018-12-10 7:32 ` Weiyi Lu
2018-12-10 7:32 ` Weiyi Lu
2018-12-10 12:52 ` Nicolas Boichat
2018-12-10 12:52 ` Nicolas Boichat
2018-12-10 7:32 ` [PATCH v3 05/12] dt-bindings: ARM: Mediatek: Document bindings for MT8183 Weiyi Lu
2018-12-10 7:32 ` Weiyi Lu
2018-12-10 7:32 ` Weiyi Lu
2018-12-14 21:57 ` Stephen Boyd
2018-12-14 21:57 ` Stephen Boyd
2018-12-14 21:57 ` Stephen Boyd
2018-12-10 7:32 ` [PATCH v3 06/12] clk: mediatek: Add dt-bindings for MT8183 clocks Weiyi Lu
2018-12-10 7:32 ` Weiyi Lu
2018-12-10 7:32 ` Weiyi Lu
2018-12-10 7:32 ` [PATCH v3 07/12] clk: mediatek: Add flags support for mtk_gate data Weiyi Lu
2018-12-10 7:32 ` Weiyi Lu
2018-12-10 7:32 ` Weiyi Lu
2018-12-10 7:32 ` [PATCH v3 08/12] clk: mediatek: Add MT8183 clock support Weiyi Lu
2018-12-10 7:32 ` Weiyi Lu
2018-12-10 7:32 ` Weiyi Lu
2018-12-11 1:00 ` Nicolas Boichat
2018-12-11 1:00 ` Nicolas Boichat
2019-02-01 8:22 ` Weiyi Lu
2019-02-01 8:22 ` Weiyi Lu
2019-02-01 8:22 ` Weiyi Lu
2018-12-14 21:59 ` Stephen Boyd [this message]
2018-12-14 21:59 ` Stephen Boyd
2018-12-14 21:59 ` Stephen Boyd
2019-02-01 8:22 ` Weiyi Lu
2019-02-01 8:22 ` Weiyi Lu
2019-02-01 8:22 ` Weiyi Lu
2018-12-10 7:32 ` [PATCH v3 09/12] dt-bindings: soc: fix typo of MT8173 power dt-bindings Weiyi Lu
2018-12-10 7:32 ` Weiyi Lu
2018-12-10 7:32 ` Weiyi Lu
2018-12-10 7:32 ` [PATCH v3 10/12] dt-bindings: soc: Add MT8183 " Weiyi Lu
2018-12-10 7:32 ` Weiyi Lu
2018-12-10 7:32 ` Weiyi Lu
2018-12-10 7:32 ` [PATCH v3 11/12] soc: mediatek: Add MT8183 scpsys support Weiyi Lu
2018-12-10 7:32 ` Weiyi Lu
2018-12-10 7:32 ` Weiyi Lu
2018-12-10 7:32 ` [PATCH v3 12/12] clk: mediatek: Allow changing PLL rate when it is off Weiyi Lu
2018-12-10 7:32 ` Weiyi Lu
2018-12-10 7:32 ` Weiyi Lu
2018-12-14 22:01 ` Stephen Boyd
2018-12-14 22:01 ` Stephen Boyd
2018-12-14 22:01 ` Stephen Boyd
2019-02-01 8:22 ` Weiyi Lu
2019-02-01 8:22 ` Weiyi Lu
2019-02-01 8:22 ` Weiyi Lu
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