From: Andrew Murray <andrew.murray@arm.com> To: Peter Zijlstra <peterz@infradead.org>, Ingo Molnar <mingo@redhat.com>, Arnaldo Carvalho de Melo <acme@kernel.org>, Richard Henderson <rth@twiddle.net>, Ivan Kokshaysky <ink@jurassic.park.msu.ru>, Matt Turner <mattst88@gmail.com>, Will Deacon <will.deacon@arm.com>, Mark Rutland <mark.rutland@arm.com>, Shawn Guo <shawnguo@kernel.org>, Sascha Hauer <s.hauer@pengutronix.de>, Benjamin Herrenschmidt <benh@kernel.crashing.org>, Paul Mackerras <paulus@samba.org>, Thomas Gleixner <tglx@linutronix.de>, Borislav Petkov <bp@alien8.de>, Russell King <linux@armlinux.org.uk>, suzuki.poulose@arm.com, robin.murphy@arm.com, Michael Ellerman <mpe@ellerman.id.au> Cc: x86@kernel.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-alpha@vger.kernel.org Subject: [PATCH v4 11/13] x86: perf/core: use PERF_PMU_CAP_NO_EXCLUDE for exclude incapable PMUs Date: Mon, 7 Jan 2019 16:27:28 +0000 [thread overview] Message-ID: <1546878450-20341-12-git-send-email-andrew.murray@arm.com> (raw) In-Reply-To: <1546878450-20341-1-git-send-email-andrew.murray@arm.com> For x86 PMUs that do not support context exclusion let's advertise the PERF_PMU_CAP_NO_EXCLUDE capability. This ensures that perf will prevent us from handling events where any exclusion flags are set. Let's also remove the now unnecessary check for exclusion flags. This change means that amd/iommu and amd/uncore will now also indicate that they do not support exclude_{hv|idle} and intel/uncore that it does not support exclude_{guest|host}. Signed-off-by: Andrew Murray <andrew.murray@arm.com> --- arch/x86/events/amd/iommu.c | 6 +----- arch/x86/events/amd/uncore.c | 7 ++----- arch/x86/events/intel/uncore.c | 9 +-------- 3 files changed, 4 insertions(+), 18 deletions(-) diff --git a/arch/x86/events/amd/iommu.c b/arch/x86/events/amd/iommu.c index 3210fee..7635c23 100644 --- a/arch/x86/events/amd/iommu.c +++ b/arch/x86/events/amd/iommu.c @@ -223,11 +223,6 @@ static int perf_iommu_event_init(struct perf_event *event) if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) return -EINVAL; - /* IOMMU counters do not have usr/os/guest/host bits */ - if (event->attr.exclude_user || event->attr.exclude_kernel || - event->attr.exclude_host || event->attr.exclude_guest) - return -EINVAL; - if (event->cpu < 0) return -EINVAL; @@ -414,6 +409,7 @@ static const struct pmu iommu_pmu __initconst = { .read = perf_iommu_read, .task_ctx_nr = perf_invalid_context, .attr_groups = amd_iommu_attr_groups, + .capabilities = PERF_PMU_CAP_NO_EXCLUDE, }; static __init int init_one_iommu(unsigned int idx) diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c index 398df6e..79cfd3b 100644 --- a/arch/x86/events/amd/uncore.c +++ b/arch/x86/events/amd/uncore.c @@ -201,11 +201,6 @@ static int amd_uncore_event_init(struct perf_event *event) if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) return -EINVAL; - /* NB and Last level cache counters do not have usr/os/guest/host bits */ - if (event->attr.exclude_user || event->attr.exclude_kernel || - event->attr.exclude_host || event->attr.exclude_guest) - return -EINVAL; - /* and we do not enable counter overflow interrupts */ hwc->config = event->attr.config & AMD64_RAW_EVENT_MASK_NB; hwc->idx = -1; @@ -307,6 +302,7 @@ static struct pmu amd_nb_pmu = { .start = amd_uncore_start, .stop = amd_uncore_stop, .read = amd_uncore_read, + .capabilities = PERF_PMU_CAP_NO_EXCLUDE, }; static struct pmu amd_llc_pmu = { @@ -317,6 +313,7 @@ static struct pmu amd_llc_pmu = { .start = amd_uncore_start, .stop = amd_uncore_stop, .read = amd_uncore_read, + .capabilities = PERF_PMU_CAP_NO_EXCLUDE, }; static struct amd_uncore *amd_uncore_alloc(unsigned int cpu) diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c index 27a4614..d516161 100644 --- a/arch/x86/events/intel/uncore.c +++ b/arch/x86/events/intel/uncore.c @@ -695,14 +695,6 @@ static int uncore_pmu_event_init(struct perf_event *event) if (pmu->func_id < 0) return -ENOENT; - /* - * Uncore PMU does measure at all privilege level all the time. - * So it doesn't make sense to specify any exclude bits. - */ - if (event->attr.exclude_user || event->attr.exclude_kernel || - event->attr.exclude_hv || event->attr.exclude_idle) - return -EINVAL; - /* Sampling not supported yet */ if (hwc->sample_period) return -EINVAL; @@ -800,6 +792,7 @@ static int uncore_pmu_register(struct intel_uncore_pmu *pmu) .stop = uncore_pmu_event_stop, .read = uncore_pmu_event_read, .module = THIS_MODULE, + .capabilities = PERF_PMU_CAP_NO_EXCLUDE, }; } else { pmu->pmu = *pmu->type->pmu; -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Andrew Murray <andrew.murray@arm.com> To: Peter Zijlstra <peterz@infradead.org>, Ingo Molnar <mingo@redhat.com>, Arnaldo Carvalho de Melo <acme@kernel.org>, Richard Henderson <rth@twiddle.net>, Ivan Kokshaysky <ink@jurassic.park.msu.ru>, Matt Turner <mattst88@gmail.com>, Will Deacon <will.deacon@arm.com>, Mark Rutland <mark.rutland@arm.com>, Shawn Guo <shawnguo@kernel.org>, Sascha Hauer <s.hauer@pengutronix.de>, Benjamin Herrenschmidt <benh@kernel.crashing.org>, Paul Mackerras <paulus@samba.org>, Thomas Gleixner <tglx@linutronix.de>, Borislav Petkov <bp@alien8.de>, Russell King <linux@armlinux.org.uk>, suzuki.poulose@arm.com, robin.murphy@arm.com, Michael Ellerman <mpe@ellerman.id.au> Cc: x86@kernel.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-alpha@vger.kernel.org Subject: [PATCH v4 11/13] x86: perf/core: use PERF_PMU_CAP_NO_EXCLUDE for exclude incapable PMUs Date: Mon, 7 Jan 2019 16:27:28 +0000 [thread overview] Message-ID: <1546878450-20341-12-git-send-email-andrew.murray@arm.com> (raw) In-Reply-To: <1546878450-20341-1-git-send-email-andrew.murray@arm.com> For x86 PMUs that do not support context exclusion let's advertise the PERF_PMU_CAP_NO_EXCLUDE capability. This ensures that perf will prevent us from handling events where any exclusion flags are set. Let's also remove the now unnecessary check for exclusion flags. This change means that amd/iommu and amd/uncore will now also indicate that they do not support exclude_{hv|idle} and intel/uncore that it does not support exclude_{guest|host}. Signed-off-by: Andrew Murray <andrew.murray@arm.com> --- arch/x86/events/amd/iommu.c | 6 +----- arch/x86/events/amd/uncore.c | 7 ++----- arch/x86/events/intel/uncore.c | 9 +-------- 3 files changed, 4 insertions(+), 18 deletions(-) diff --git a/arch/x86/events/amd/iommu.c b/arch/x86/events/amd/iommu.c index 3210fee..7635c23 100644 --- a/arch/x86/events/amd/iommu.c +++ b/arch/x86/events/amd/iommu.c @@ -223,11 +223,6 @@ static int perf_iommu_event_init(struct perf_event *event) if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) return -EINVAL; - /* IOMMU counters do not have usr/os/guest/host bits */ - if (event->attr.exclude_user || event->attr.exclude_kernel || - event->attr.exclude_host || event->attr.exclude_guest) - return -EINVAL; - if (event->cpu < 0) return -EINVAL; @@ -414,6 +409,7 @@ static const struct pmu iommu_pmu __initconst = { .read = perf_iommu_read, .task_ctx_nr = perf_invalid_context, .attr_groups = amd_iommu_attr_groups, + .capabilities = PERF_PMU_CAP_NO_EXCLUDE, }; static __init int init_one_iommu(unsigned int idx) diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c index 398df6e..79cfd3b 100644 --- a/arch/x86/events/amd/uncore.c +++ b/arch/x86/events/amd/uncore.c @@ -201,11 +201,6 @@ static int amd_uncore_event_init(struct perf_event *event) if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) return -EINVAL; - /* NB and Last level cache counters do not have usr/os/guest/host bits */ - if (event->attr.exclude_user || event->attr.exclude_kernel || - event->attr.exclude_host || event->attr.exclude_guest) - return -EINVAL; - /* and we do not enable counter overflow interrupts */ hwc->config = event->attr.config & AMD64_RAW_EVENT_MASK_NB; hwc->idx = -1; @@ -307,6 +302,7 @@ static struct pmu amd_nb_pmu = { .start = amd_uncore_start, .stop = amd_uncore_stop, .read = amd_uncore_read, + .capabilities = PERF_PMU_CAP_NO_EXCLUDE, }; static struct pmu amd_llc_pmu = { @@ -317,6 +313,7 @@ static struct pmu amd_llc_pmu = { .start = amd_uncore_start, .stop = amd_uncore_stop, .read = amd_uncore_read, + .capabilities = PERF_PMU_CAP_NO_EXCLUDE, }; static struct amd_uncore *amd_uncore_alloc(unsigned int cpu) diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c index 27a4614..d516161 100644 --- a/arch/x86/events/intel/uncore.c +++ b/arch/x86/events/intel/uncore.c @@ -695,14 +695,6 @@ static int uncore_pmu_event_init(struct perf_event *event) if (pmu->func_id < 0) return -ENOENT; - /* - * Uncore PMU does measure at all privilege level all the time. - * So it doesn't make sense to specify any exclude bits. - */ - if (event->attr.exclude_user || event->attr.exclude_kernel || - event->attr.exclude_hv || event->attr.exclude_idle) - return -EINVAL; - /* Sampling not supported yet */ if (hwc->sample_period) return -EINVAL; @@ -800,6 +792,7 @@ static int uncore_pmu_register(struct intel_uncore_pmu *pmu) .stop = uncore_pmu_event_stop, .read = uncore_pmu_event_read, .module = THIS_MODULE, + .capabilities = PERF_PMU_CAP_NO_EXCLUDE, }; } else { pmu->pmu = *pmu->type->pmu; -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-01-07 16:28 UTC|newest] Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-01-07 16:27 [PATCH v4 00/13] perf/core: Generalise event exclusion checking Andrew Murray 2019-01-07 16:27 ` Andrew Murray 2019-01-07 16:27 ` [PATCH v4 01/13] perf/doc: update design.txt for exclude_{host|guest} flags Andrew Murray 2019-01-07 16:27 ` Andrew Murray 2019-01-07 16:27 ` [PATCH v4 02/13] perf/core: add function to test for event exclusion flags Andrew Murray 2019-01-07 16:27 ` Andrew Murray 2019-01-07 16:27 ` [PATCH v4 03/13] perf/core: add PERF_PMU_CAP_NO_EXCLUDE for exclusion incapable PMUs Andrew Murray 2019-01-07 16:27 ` Andrew Murray 2019-01-07 16:27 ` [PATCH v4 04/13] alpha: perf/core: use PERF_PMU_CAP_NO_EXCLUDE Andrew Murray 2019-01-07 16:27 ` Andrew Murray 2019-01-07 16:27 ` [PATCH v4 05/13] arm: perf: conditionally " Andrew Murray 2019-01-07 16:27 ` Andrew Murray 2019-01-08 10:28 ` Peter Zijlstra 2019-01-08 10:28 ` Peter Zijlstra 2019-01-08 10:28 ` Peter Zijlstra 2019-01-08 10:28 ` Peter Zijlstra 2019-01-08 13:07 ` Andrew Murray 2019-01-08 13:07 ` Andrew Murray 2019-01-08 13:07 ` Andrew Murray 2019-01-08 13:10 ` Peter Zijlstra 2019-01-08 13:10 ` Peter Zijlstra 2019-01-08 13:10 ` Peter Zijlstra 2019-01-08 13:10 ` Peter Zijlstra 2019-01-08 13:13 ` Andrew Murray 2019-01-08 13:13 ` Andrew Murray 2019-01-08 13:13 ` Andrew Murray 2019-01-08 14:43 ` Peter Zijlstra 2019-01-08 14:43 ` Peter Zijlstra 2019-01-08 14:43 ` Peter Zijlstra 2019-01-08 14:43 ` Peter Zijlstra 2019-01-07 16:27 ` [PATCH v4 06/13] arm: perf/core: use PERF_PMU_CAP_NO_EXCLUDE for exclude incapable PMUs Andrew Murray 2019-01-07 16:27 ` Andrew Murray 2019-01-07 16:27 ` [PATCH v4 07/13] drivers/perf: " Andrew Murray 2019-01-07 16:27 ` Andrew Murray 2019-01-07 16:27 ` [PATCH v4 08/13] " Andrew Murray 2019-01-07 16:27 ` Andrew Murray 2019-01-07 16:27 ` [PATCH v4 09/13] powerpc: " Andrew Murray 2019-01-07 16:27 ` Andrew Murray 2019-01-07 16:27 ` [PATCH v4 10/13] x86: " Andrew Murray 2019-01-07 16:27 ` Andrew Murray 2019-01-08 10:48 ` Peter Zijlstra 2019-01-08 10:48 ` Peter Zijlstra 2019-01-08 10:48 ` Peter Zijlstra 2019-01-08 10:48 ` Peter Zijlstra 2019-01-08 13:12 ` Andrew Murray 2019-01-08 13:12 ` Andrew Murray 2019-01-08 13:12 ` Andrew Murray 2019-01-08 13:12 ` Andrew Murray 2019-01-08 16:36 ` Boris Ostrovsky 2019-01-08 16:36 ` Boris Ostrovsky 2019-01-08 16:36 ` Boris Ostrovsky 2019-01-08 16:36 ` Boris Ostrovsky 2019-01-08 18:49 ` Peter Zijlstra 2019-01-08 18:49 ` Peter Zijlstra 2019-01-08 18:49 ` Peter Zijlstra 2019-01-08 18:49 ` Peter Zijlstra 2019-01-10 13:15 ` Michael Ellerman 2019-01-10 13:15 ` Michael Ellerman 2019-01-10 13:15 ` Michael Ellerman 2019-01-10 13:15 ` Michael Ellerman 2019-01-07 16:27 ` Andrew Murray [this message] 2019-01-07 16:27 ` [PATCH v4 11/13] " Andrew Murray 2019-01-08 10:49 ` Peter Zijlstra 2019-01-08 10:49 ` Peter Zijlstra 2019-01-08 10:49 ` Peter Zijlstra 2019-01-08 10:49 ` Peter Zijlstra 2019-01-08 13:08 ` Andrew Murray 2019-01-08 13:08 ` Andrew Murray 2019-01-08 13:08 ` Andrew Murray 2019-01-07 16:27 ` [PATCH v4 12/13] perf/core: remove unused perf_flags Andrew Murray 2019-01-07 16:27 ` Andrew Murray 2019-01-07 16:27 ` [PATCH v4 13/13] drivers/perf: use PERF_PMU_CAP_NO_EXCLUDE for Cavium TX2 PMU Andrew Murray 2019-01-07 16:27 ` Andrew Murray 2019-01-10 11:10 ` Will Deacon 2019-01-10 11:10 ` Will Deacon 2019-01-10 11:10 ` Will Deacon
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=1546878450-20341-12-git-send-email-andrew.murray@arm.com \ --to=andrew.murray@arm.com \ --cc=acme@kernel.org \ --cc=benh@kernel.crashing.org \ --cc=bp@alien8.de \ --cc=ink@jurassic.park.msu.ru \ --cc=linux-alpha@vger.kernel.org \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux@armlinux.org.uk \ --cc=linuxppc-dev@lists.ozlabs.org \ --cc=mark.rutland@arm.com \ --cc=mattst88@gmail.com \ --cc=mingo@redhat.com \ --cc=mpe@ellerman.id.au \ --cc=paulus@samba.org \ --cc=peterz@infradead.org \ --cc=robin.murphy@arm.com \ --cc=rth@twiddle.net \ --cc=s.hauer@pengutronix.de \ --cc=shawnguo@kernel.org \ --cc=suzuki.poulose@arm.com \ --cc=tglx@linutronix.de \ --cc=will.deacon@arm.com \ --cc=x86@kernel.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.