From: Sowjanya Komatineni <skomatineni@nvidia.com>
To: adrian.hunter@intel.com, ulf.hansson@linaro.org,
robh+dt@kernel.org, mark.rutland@arm.com, riteshh@codeaurora.org
Cc: skomatineni@nvidia.com, thierry.reding@gmail.com,
jonathanh@nvidia.com, anrao@nvidia.com,
linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-mmc@vger.kernel.org, devicetree@vger.kernel.org
Subject: [PATCH V4 08/10] mmc: cqhci: add CQHCI_SSC1 register CBC field mask
Date: Sat, 23 Mar 2019 21:45:25 -0700 [thread overview]
Message-ID: <1553402727-23130-8-git-send-email-skomatineni@nvidia.com> (raw)
In-Reply-To: <1553402727-23130-1-git-send-email-skomatineni@nvidia.com>
This patch adds define for CBC field mask of the register
CQHCI_SSC1.
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
drivers/mmc/host/cqhci.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mmc/host/cqhci.h b/drivers/mmc/host/cqhci.h
index 928ec491eecf..1e8e01d81015 100644
--- a/drivers/mmc/host/cqhci.h
+++ b/drivers/mmc/host/cqhci.h
@@ -88,6 +88,7 @@
/* send status config 1 */
#define CQHCI_SSC1 0x40
+#define CQHCI_SSC1_CBC_MASK GENMASK(19, 16)
/* send status config 2 */
#define CQHCI_SSC2 0x44
--
2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Sowjanya Komatineni <skomatineni@nvidia.com>
To: <adrian.hunter@intel.com>, <ulf.hansson@linaro.org>,
<robh+dt@kernel.org>, <mark.rutland@arm.com>,
<riteshh@codeaurora.org>
Cc: <skomatineni@nvidia.com>, <thierry.reding@gmail.com>,
<jonathanh@nvidia.com>, <anrao@nvidia.com>,
<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-mmc@vger.kernel.org>, <devicetree@vger.kernel.org>
Subject: [PATCH V4 08/10] mmc: cqhci: add CQHCI_SSC1 register CBC field mask
Date: Sat, 23 Mar 2019 21:45:25 -0700 [thread overview]
Message-ID: <1553402727-23130-8-git-send-email-skomatineni@nvidia.com> (raw)
In-Reply-To: <1553402727-23130-1-git-send-email-skomatineni@nvidia.com>
This patch adds define for CBC field mask of the register
CQHCI_SSC1.
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
drivers/mmc/host/cqhci.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mmc/host/cqhci.h b/drivers/mmc/host/cqhci.h
index 928ec491eecf..1e8e01d81015 100644
--- a/drivers/mmc/host/cqhci.h
+++ b/drivers/mmc/host/cqhci.h
@@ -88,6 +88,7 @@
/* send status config 1 */
#define CQHCI_SSC1 0x40
+#define CQHCI_SSC1_CBC_MASK GENMASK(19, 16)
/* send status config 2 */
#define CQHCI_SSC2 0x44
--
2.7.4
next prev parent reply other threads:[~2019-03-24 4:45 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-24 4:45 [PATCH V4 01/10] mmc: tegra: fix ddr signaling for non-ddr modes Sowjanya Komatineni
2019-03-24 4:45 ` Sowjanya Komatineni
2019-03-24 4:45 ` [PATCH V4 02/10] mmc: sdhci: allow host to specify maximum tuning loops Sowjanya Komatineni
2019-03-24 4:45 ` Sowjanya Komatineni
2019-03-25 10:25 ` Adrian Hunter
2019-03-24 4:45 ` [PATCH V4 03/10] mmc: tegra: update hw tuning process Sowjanya Komatineni
2019-03-24 4:45 ` Sowjanya Komatineni
2019-03-25 10:38 ` Adrian Hunter
2019-03-24 4:45 ` [PATCH V4 04/10] dt-bindings: mmc: tegra: document Tegra194 compatible string Sowjanya Komatineni
2019-03-24 4:45 ` Sowjanya Komatineni
2019-03-24 4:45 ` [PATCH V4 05/10] arm64: tegra: fix default tap and trim values Sowjanya Komatineni
2019-03-24 4:45 ` Sowjanya Komatineni
2019-03-24 4:45 ` [PATCH V4 06/10] mmc: cqhci: allow hosts to update dcmd cmd desc Sowjanya Komatineni
2019-03-24 4:45 ` Sowjanya Komatineni
2019-03-25 10:39 ` Adrian Hunter
2019-03-24 4:45 ` [PATCH V4 07/10] mmc: tegra: add Tegra186 WAR for CQE Sowjanya Komatineni
2019-03-24 4:45 ` Sowjanya Komatineni
2019-03-25 10:41 ` Adrian Hunter
2019-03-24 4:45 ` Sowjanya Komatineni [this message]
2019-03-24 4:45 ` [PATCH V4 08/10] mmc: cqhci: add CQHCI_SSC1 register CBC field mask Sowjanya Komatineni
2019-03-24 4:45 ` [PATCH V4 09/10] mmc: tegra: fix CQE enable and resume sequence Sowjanya Komatineni
2019-03-24 4:45 ` Sowjanya Komatineni
2019-03-24 4:45 ` [PATCH V4 10/10] arm64: tegra: enable command queue for tegra186 sdmmc4 Sowjanya Komatineni
2019-03-24 4:45 ` Sowjanya Komatineni
2019-03-25 13:27 ` [PATCH V4 01/10] mmc: tegra: fix ddr signaling for non-ddr modes Ulf Hansson
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