From: Wu Hao <hao.wu@intel.com>
To: mdf@kernel.org, linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: linux-api@vger.kernel.org, yilun.xu@intel.com, hao.wu@intel.com,
gregkh@linuxfoundation.org, atull@kernel.org
Subject: [PATCH v4 01/15] fpga: dfl-fme-mgr: fix FME_PR_INTFC_ID register address.
Date: Thu, 27 Jun 2019 12:44:41 +0800 [thread overview]
Message-ID: <1561610695-5414-2-git-send-email-hao.wu@intel.com> (raw)
In-Reply-To: <1561610695-5414-1-git-send-email-hao.wu@intel.com>
FME_PR_INTFC_ID is used as compat_id for fpga manager and region,
but high 64 bits and low 64 bits of the compat_id are swapped by
mistake. This patch fixes this problem by fixing register address.
Signed-off-by: Wu Hao <hao.wu@intel.com>
Acked-by: Alan Tull <atull@kernel.org>
Acked-by: Moritz Fischer <mdf@kernel.org>
---
drivers/fpga/dfl-fme-mgr.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/fpga/dfl-fme-mgr.c b/drivers/fpga/dfl-fme-mgr.c
index 76f3770..b3f7eee 100644
--- a/drivers/fpga/dfl-fme-mgr.c
+++ b/drivers/fpga/dfl-fme-mgr.c
@@ -30,8 +30,8 @@
#define FME_PR_STS 0x10
#define FME_PR_DATA 0x18
#define FME_PR_ERR 0x20
-#define FME_PR_INTFC_ID_H 0xA8
-#define FME_PR_INTFC_ID_L 0xB0
+#define FME_PR_INTFC_ID_L 0xA8
+#define FME_PR_INTFC_ID_H 0xB0
/* FME PR Control Register Bitfield */
#define FME_PR_CTRL_PR_RST BIT_ULL(0) /* Reset PR engine */
--
1.8.3.1
next prev parent reply other threads:[~2019-06-27 5:01 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-27 4:44 [PATCH v4 00/15] add new features for FPGA DFL drivers Wu Hao
2019-06-27 4:44 ` Wu Hao [this message]
2019-06-27 4:44 ` [PATCH v4 02/15] fpga: dfl: fme: remove copy_to_user() in ioctl for PR Wu Hao
2019-06-27 4:44 ` [PATCH v4 03/15] fpga: dfl: fme: align PR buffer size per PR datawidth Wu Hao
2019-06-27 4:44 ` [PATCH v4 04/15] fpga: dfl: fme: support 512bit data width PR Wu Hao
2019-06-27 4:44 ` [PATCH v4 05/15] Documentation: fpga: dfl: add descriptions for virtualization and new interfaces Wu Hao
2019-06-28 1:12 ` Moritz Fischer
2019-06-28 1:12 ` Moritz Fischer
2019-06-28 2:13 ` Wu Hao
2019-07-01 6:30 ` Wu Hao
2019-06-27 4:44 ` [PATCH v4 06/15] fpga: dfl: fme: add DFL_FPGA_FME_PORT_RELEASE/ASSIGN ioctl support Wu Hao
2019-06-27 4:44 ` [PATCH v4 07/15] fpga: dfl: pci: enable SRIOV support Wu Hao
2019-06-27 4:44 ` [PATCH v4 08/15] fpga: dfl: afu: add AFU state related sysfs interfaces Wu Hao
2019-06-27 4:44 ` [PATCH v4 09/15] fpga: dfl: afu: add userclock " Wu Hao
2019-06-27 4:44 ` [PATCH v4 10/15] fpga: dfl: add id_table for dfl private feature driver Wu Hao
2019-06-27 4:44 ` [PATCH v4 11/15] fpga: dfl: afu: export __port_enable/disable function Wu Hao
2019-06-27 4:44 ` [PATCH v4 12/15] fpga: dfl: afu: add error reporting support Wu Hao
2019-06-27 4:44 ` [PATCH v4 13/15] fpga: dfl: afu: add STP (SignalTap) support Wu Hao
2019-06-27 4:44 ` [PATCH v4 14/15] fpga: dfl: fme: add capability sysfs interfaces Wu Hao
2019-06-27 4:44 ` [PATCH v4 15/15] fpga: dfl: fme: add global error reporting support Wu Hao
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