From: Wu Hao <hao.wu@intel.com>
To: mdf@kernel.org, linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: linux-api@vger.kernel.org, yilun.xu@intel.com, hao.wu@intel.com,
gregkh@linuxfoundation.org, atull@kernel.org
Subject: [PATCH v4 03/15] fpga: dfl: fme: align PR buffer size per PR datawidth
Date: Thu, 27 Jun 2019 12:44:43 +0800 [thread overview]
Message-ID: <1561610695-5414-4-git-send-email-hao.wu@intel.com> (raw)
In-Reply-To: <1561610695-5414-1-git-send-email-hao.wu@intel.com>
Current driver checks if input bitstream file size is aligned or
not per PR data width (default 32bits). It requires one additional
step for end user when they generate the bitstream file, padding
extra zeros to bitstream file to align its size per PR data width,
but they don't have to as hardware will drop extra padding bytes
automatically.
In order to simplify the user steps, this patch aligns PR buffer
size per PR data width in driver, to allow user to pass unaligned
size bitstream files to driver.
Signed-off-by: Xu Yilun <yilun.xu@intel.com>
Signed-off-by: Wu Hao <hao.wu@intel.com>
Acked-by: Alan Tull <atull@kernel.org>
Acked-by: Moritz Fischer <mdf@kernel.org>
---
drivers/fpga/dfl-fme-pr.c | 14 +++++++++-----
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/fpga/dfl-fme-pr.c b/drivers/fpga/dfl-fme-pr.c
index 6ec0f09..3c71dc3 100644
--- a/drivers/fpga/dfl-fme-pr.c
+++ b/drivers/fpga/dfl-fme-pr.c
@@ -74,6 +74,7 @@ static int fme_pr(struct platform_device *pdev, unsigned long arg)
struct dfl_fme *fme;
unsigned long minsz;
void *buf = NULL;
+ size_t length;
int ret = 0;
u64 v;
@@ -85,9 +86,6 @@ static int fme_pr(struct platform_device *pdev, unsigned long arg)
if (port_pr.argsz < minsz || port_pr.flags)
return -EINVAL;
- if (!IS_ALIGNED(port_pr.buffer_size, 4))
- return -EINVAL;
-
/* get fme header region */
fme_hdr = dfl_get_feature_ioaddr_by_id(&pdev->dev,
FME_FEATURE_ID_HEADER);
@@ -103,7 +101,13 @@ static int fme_pr(struct platform_device *pdev, unsigned long arg)
port_pr.buffer_size))
return -EFAULT;
- buf = vmalloc(port_pr.buffer_size);
+ /*
+ * align PR buffer per PR bandwidth, as HW ignores the extra padding
+ * data automatically.
+ */
+ length = ALIGN(port_pr.buffer_size, 4);
+
+ buf = vmalloc(length);
if (!buf)
return -ENOMEM;
@@ -140,7 +144,7 @@ static int fme_pr(struct platform_device *pdev, unsigned long arg)
fpga_image_info_free(region->info);
info->buf = buf;
- info->count = port_pr.buffer_size;
+ info->count = length;
info->region_id = port_pr.port_id;
region->info = info;
--
1.8.3.1
next prev parent reply other threads:[~2019-06-27 5:02 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-27 4:44 [PATCH v4 00/15] add new features for FPGA DFL drivers Wu Hao
2019-06-27 4:44 ` [PATCH v4 01/15] fpga: dfl-fme-mgr: fix FME_PR_INTFC_ID register address Wu Hao
2019-06-27 4:44 ` [PATCH v4 02/15] fpga: dfl: fme: remove copy_to_user() in ioctl for PR Wu Hao
2019-06-27 4:44 ` Wu Hao [this message]
2019-06-27 4:44 ` [PATCH v4 04/15] fpga: dfl: fme: support 512bit data width PR Wu Hao
2019-06-27 4:44 ` [PATCH v4 05/15] Documentation: fpga: dfl: add descriptions for virtualization and new interfaces Wu Hao
2019-06-28 1:12 ` Moritz Fischer
2019-06-28 1:12 ` Moritz Fischer
2019-06-28 2:13 ` Wu Hao
2019-07-01 6:30 ` Wu Hao
2019-06-27 4:44 ` [PATCH v4 06/15] fpga: dfl: fme: add DFL_FPGA_FME_PORT_RELEASE/ASSIGN ioctl support Wu Hao
2019-06-27 4:44 ` [PATCH v4 07/15] fpga: dfl: pci: enable SRIOV support Wu Hao
2019-06-27 4:44 ` [PATCH v4 08/15] fpga: dfl: afu: add AFU state related sysfs interfaces Wu Hao
2019-06-27 4:44 ` [PATCH v4 09/15] fpga: dfl: afu: add userclock " Wu Hao
2019-06-27 4:44 ` [PATCH v4 10/15] fpga: dfl: add id_table for dfl private feature driver Wu Hao
2019-06-27 4:44 ` [PATCH v4 11/15] fpga: dfl: afu: export __port_enable/disable function Wu Hao
2019-06-27 4:44 ` [PATCH v4 12/15] fpga: dfl: afu: add error reporting support Wu Hao
2019-06-27 4:44 ` [PATCH v4 13/15] fpga: dfl: afu: add STP (SignalTap) support Wu Hao
2019-06-27 4:44 ` [PATCH v4 14/15] fpga: dfl: fme: add capability sysfs interfaces Wu Hao
2019-06-27 4:44 ` [PATCH v4 15/15] fpga: dfl: fme: add global error reporting support Wu Hao
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